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7.8.1.25 SELFTESTCYC Register (Offset = 1048h) [reset = 0h]
SELFTESTCYC is shown in
Internal. Only to be used through TI provided API.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit
Field
31-0
CYCLES
SWCU117C – February 2015 – Revised September 2015
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Figure 7-34
and described in
Figure 7-34. SELFTESTCYC Register
CYCLES
R/W-0h
Table 7-28. SELFTESTCYC Register Field Descriptions
Type
Reset
R/W
0h
Copyright © 2015, Texas Instruments Incorporated
Table
7-28.
9
Description
Internal. Only to be used through TI provided API.
Versatile Instruction Memory System (VIMS)
VIMS Registers
8
7
6
5
4
3
2
1
0
571