Texas Instruments SimpleLink CC2620 Technical Reference Manual page 174

Cortex-M3 Processor Registers
2.7.4.33 SHPR2 Register (Offset = D1Ch) [reset = 0h]
SHPR2 is shown in
System Handlers 8-11 Priority
This register is used to prioritize the SVC handler. System Handlers are a special class of exception
handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off
(disabled). When disabled, the fault is always treated as a Hard Fault.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PRI_11
R/W-0h
Bit Field
31-24 PRI_11
23-0 RESERVED
174
Figure 2-103 and described in
Figure 2-103. SHPR2 Register
Table 2-129. SHPR2 Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-129.
9
RESERVED
R/W-0h
Description
Priority of system handler 11. SVCall
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
SWCU117C – February 2015 – Revised September 2015
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