Cortex-M3 System Component Details - Texas Instruments SimpleLink CC2620 Technical Reference Manual

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The flash patch and breakpoint unit (FPB) provides up to eight hardware-breakpoint comparators that
debuggers can use. The comparators in the FPB also provide remap functions of up to eight words in the
program code in the CODE memory region. Remap functions enable patching of applications stored in a
read-only area of flash memory into another area of on-chip SRAM or flash memory. If a patch is required,
the application programs the FPB to remap a number of addresses. When those addresses are accessed,
the accesses are redirected to a remap table specified in the FPB configuration.
For more information on the Cortex-M3 debug capabilities, see the ARM
Specification.
2.3.3 Trace Port Interface Unit
Figure 2-2 shows the trace port interface unit (TPIU) block diagram. The TPIU acts as a bridge between
the Cortex-M3 trace data from the ITM, and an off-chip trace port analyzer.
Debug ATB
Slave Port
APB Slave
Port
See CM3_TIPROP

2.3.4 Cortex-M3 System Component Details

The Cortex-M3 includes the following system components:
• SysTick: A 24-bit count-down timer that can be used as a real-time operating system (RTOS) tick
timer or as a simple counter (see
• Nested Vectored Interrupt Controller: An embedded interrupt controller (INTC) that supports low-
latency interrupt processing (see
• System Control Block: The programming model interface to the processor, which provides system
implementation information and system control, including configuration, control, and reporting of
system exceptions (see
managed centrally in SCB within the system control space (SCS).
2.4 Programming Model
This section describes the Cortex-M3 programming model. For more information about the processor
modes and privilege levels for software execution and stacks and for descriptions of the individual core
registers, see Section
SWCU117C – February 2015 – Revised September 2015
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Figure 2-2. TPIU Block Diagram
ATB
Asynchronous FIFO
Interface
APB
Interface
for more information.
Section
Section
Section 3.2.3, SCB). Key control and status features of the processor are
2.5, Coretex-M3 Core Registers.
Copyright © 2015, Texas Instruments Incorporated
Trace Out
(Serializer)
3.2.1, SysTick)
3.2.2, NVIC)
®
Debug Interface V5 Architecture
CPU_TIPROP_TRACECLKMUX
Register
Serial Wire
Viewer (SWV)
To IOC
Trace Clock
Trace Data
The Cortex-M3 Processor
Overview
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