Texas Instruments SimpleLink CC2620 Technical Reference Manual page 477

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6.2.4.3 INFRCLKDIVDS Register (Offset = 8h) [reset = 0h]
INFRCLKDIVDS is shown in
Infrastructure Clock Division Factor For DeepSleep Mode
31 30 29 28
15 14 13 12
Bit Field
31-2 RESERVED
1-0 RATIO
SWCU117C – February 2015 – Revised September 2015
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Figure 6-42 and described in
Figure 6-42. INFRCLKDIVDS Register
27 26 25 24
RESERVED
R-0h
11 10 9 8
RESERVED
R-0h
Table 6-47. INFRCLKDIVDS Register Field Descriptions
Type Reset
R 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 6-47.
23 22 21 20
7 6 5 4
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Division rate for clocks driving modules in the MCU_AON domain
when system CPU is in seepsleep mode. Division ratio affects both
infrastructure clock and perbusull clock.
0h = Divide by 1
1h = Divide by 2
2h = Divide by 8
3h = Divide by 32
Power, Reset, and Clock Management
PRCM Registers
19 18 17 16
3 2 1 0
RATIO
R/W-0h
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