Texas Instruments SimpleLink CC2620 Technical Reference Manual page 392

Top Level Debug System
The IEEE 1149.1 TAP uses the following signals to support the operation:
• TCK (Test Clock): This signal synchronizes the internal state machine operations.
• TMS (Test Mode Select): This signal is sampled at the rising edge of TCK to determine the next state.
• TDI (Test Data In): This signal represents the data shifted into the test or programming logic of the
device. TDI is sampled at the rising edge of TCK when the internal state machine is in the correct
state.
• TDO (Test Data Out): This signal represents the data shifted out of the test or programming logic of
the device and is valid on the falling edge of TCK when the internal state machine is in the correct
state.
There is no dedicated I/O pin for TRST. The debug subsystem is reset with system-wide resets and
power-on reset.
The TAP controller, a state machine whose transitions are controlled by the TMS signal, controls the
behavior of the JTAG system.
Every state has two exits, so all transitions can be controlled by the single TMS signal sampled on TCK.
The two main paths allow for setting or retrieving information from either a data register (DR) or the
instruction register (IR) of the device. The data register depends on the value loaded into the instruction
register.
392
JTAG Interface
Figure 5-2 shows the state-transition diagram for JTAG.
Figure 5-2. JTAG State Machine
TMS=1
Test Logic Reset
TMS=0
TMS=0
Run Test Idle
TMS=1
Select DR Scan
TMS=0
TMS=1
Capture DR
TMS=0
TMS=0
Shift DR
TMS=1
TMS=1
Exit 1 DR
TMS=0
TMS=0
Pause DR
TMS=1
Exit 2 DR
TMS=1
Update DR
TMS=0
TMS=1
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Select IR Scan
TMS=1
TMS=0
Capture IR
TMS=0
TMS=0
Shift IR
TMS=1
TMS=1
Exit 1 IR
TMS=0
TMS=0
Pause IR
TMS=1
Exit 2 IR
TMS=0
TMS=1
Update IR
TMS=1 TMS=0
SWCU117C – February 2015 – Revised September 2015
www.ti.com
TMS=1
TMS=1
TMS=0
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