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7.8.1.35 FBFALLBACK Register (Offset = 2040h) [reset = 505FFFFh]
FBFALLBACK is shown in
Internal. Only to be used through TI provided API.
31
30
RESERVED
23
22
RESERVED
15
14
BANKPWR7
R/W-3h
7
6
BANKPWR3
R/W-3h
Bit
Field
31-28
RESERVED
27-24
FSM_PWRSAV
23-20
RESERVED
19-16
REG_PWRSAV
15-14
BANKPWR7
13-12
BANKPWR6
11-10
BANKPWR5
9-8
BANKPWR4
7-6
BANKPWR3
5-4
BANKPWR2
3-2
BANKPWR1
1-0
BANKPWR0
SWCU117C – February 2015 – Revised September 2015
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Figure 7-44
and described in
Figure 7-44. FBFALLBACK Register
29
28
R-0h
21
20
R-0h
13
12
BANKPWR6
R/W-3h
5
4
BANKPWR2
R/W-3h
Table 7-38. FBFALLBACK Register Field Descriptions
Type
Reset
R
0h
R/W
5h
R
0h
R/W
5h
R/W
3h
R/W
3h
R/W
3h
R/W
3h
R/W
3h
R/W
3h
R/W
3h
R/W
3h
Copyright © 2015, Texas Instruments Incorporated
Table
7-38.
27
26
FSM_PWRSAV
R/W-5h
19
18
REG_PWRSAV
R/W-5h
11
10
BANKPWR5
R/W-3h
3
2
BANKPWR1
R/W-3h
Description
Internal. Only to be used through TI provided API.
Internal. Only to be used through TI provided API.
Internal. Only to be used through TI provided API.
Internal. Only to be used through TI provided API.
Internal. Only to be used through TI provided API.
Internal. Only to be used through TI provided API.
Internal. Only to be used through TI provided API.
Internal. Only to be used through TI provided API.
Internal. Only to be used through TI provided API.
Internal. Only to be used through TI provided API.
Internal. Only to be used through TI provided API.
Internal. Only to be used through TI provided API.
Versatile Instruction Memory System (VIMS)
VIMS Registers
25
24
17
16
9
8
BANKPWR4
R/W-3h
1
0
BANKPWR0
R/W-3h
581