Texas Instruments SimpleLink CC2620 Technical Reference Manual page 341

www.ti.com
4.7.2.56 UDMACH3BSEL Register (Offset = 51Ch) [reset = 28h]
UDMACH3BSEL is shown in
Output Selection for DMA Channel 3 REQ
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Field
31-7 RESERVED
6-0 EV
SWCU117C – February 2015 – Revised September 2015
Submit Documentation Feedback
Figure 4-65 and described in
Figure 4-65. UDMACH3BSEL Register
RESERVED
R-0h
Table 4-70. UDMACH3BSEL Register Field Descriptions
Type Reset
R 0h
R 28h
Copyright © 2015, Texas Instruments Incorporated
Table 4-70.
9
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Read only selection value
28h = SSI0 RX DMA burst request , controlled by
SSI0:DMACR.RXDMAE
Interrupts and Events Registers
8 7 6 5 4 3 2 1
EV
R-28h
Interrupts and Events
0
341