Texas Instruments SimpleLink CC2620 Technical Reference Manual page 142

Cortex-M3 Processor Registers
Table 2-105. NVIC_ICER0 Register Field Descriptions (continued)
Bit Field
2 CLRENA2
1 CLRENA1
0 CLRENA0
142
Type Reset Description
R/W 0h
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details).
Reading the bit returns its current enable state.
R/W 0h
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details).
Reading the bit returns its current enable state.
R/W 0h
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details).
Reading the bit returns its current enable state.
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SWCU117C – February 2015 – Revised September 2015
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