Texas Instruments SimpleLink CC2620 Technical Reference Manual page 214

Cortex-M3 Processor Registers
2.7.5.7 FSCR Register (Offset = 308h) [reset = 0h]
FSCR is shown in
Formatter Synchronization Counter
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Field
31-0 FSCR
214
Figure 2-137 and described in
Figure 2-137. FSCR Register
Table 2-164. FSCR Register Field Descriptions
Type Reset
R 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-164.
9
FSCR
R-0h
Description
The global synchronization trigger is generated by the Program
Counter (PC) Sampler block. This means that there is no
synchronization counter in the TPIU.
SWCU117C – February 2015 – Revised September 2015
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