Texas Instruments SimpleLink CC2620 Technical Reference Manual page 154

Cortex-M3 Processor Registers
Table 2-111. NVIC_IABR0 Register Field Descriptions (continued)
Bit Field
2 ACTIVE2
1 ACTIVE1
0 ACTIVE0
154
Type Reset Description
R 0h
Reading 0 from this bit implies that interrupt line 2 is not active.
Reading 1 from this bit implies that the interrupt line 2 is active (See
EVENT:CPUIRQSEL2.EV for details).
R 0h
Reading 0 from this bit implies that interrupt line 1 is not active.
Reading 1 from this bit implies that the interrupt line 1 is active (See
EVENT:CPUIRQSEL1.EV for details).
R 0h
Reading 0 from this bit implies that interrupt line 0 is not active.
Reading 1 from this bit implies that the interrupt line 0 is active (See
EVENT:CPUIRQSEL0.EV for details).
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SWCU117C – February 2015 – Revised September 2015
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