Exception Priorities - Texas Instruments SimpleLink CC2620 Technical Reference Manual

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4.1.5 Exception Priorities

As Table 4-1 shows, all exceptions have an associated priority, with a lower priority value indicating a
higher priority and configurable priorities for all exceptions except reset, and hard fault. If software does
not configure any priorities, then all exceptions with a configurable priority have a priority of 0. For
information about configuring exception priorities, see the System Handlers Priority Registers
(CPU_SCS:SHPRn) listed in and the Interrupt Priority Registers (CPU_SCS:NVIC_IPRn) listed in .
NOTE: Configurable priority values for the CC26xx and CC13xx implementation are in the range
from 0 to 7. This means that the Reset and Hard fault exceptions, with fixed negative priority
values, always have a higher priority than any other exception.
Assigning a higher priority value to IRQ[0] and a lower-priority value to IRQ[1], for example, means that
IRQ[1] has higher priority than IRQ[0]. If IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before
IRQ[0].
If multiple pending exceptions have the same priority, the pending exception with the lowest exception
number takes precedence. For example, if IRQ[0] and IRQ[1] are pending and have the same priority,
then IRQ[0] is processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is preempted if a higher
priority exception occurs. If an exception occurs with the same priority as the exception being handled, the
handler is not preempted, irrespective of the exception number. However, the status of the new interrupt
changes to pending.
4.1.6 Interrupt Priority Grouping
To increase priority control in systems with interrupts, the NVIC supports priority grouping. This grouping
divides each interrupt priority register entry into two fields:
• An upper field that defines the group priority
• A lower field that defines a subpriority within the group
Only the group priority determines preemption of interrupt exceptions. When the processor is executing an
interrupt exception handler, another interrupt with the same group priority as the interrupt being handled
does not preempt the handler.
If multiple pending interrupts have the same group priority, the subpriority field determines the order in
which they are processed. If multiple pending interrupts have the same group priority and subpriority, the
interrupt with the lowest IRQ number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority, see Application
Interrupt/Reset Control (CPU_SCS:AIRCR) in
X].
SWCU117C – February 2015 – Revised September 2015
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Section 2.7.4.29, AIRCR Register (Offset = D0Ch) [reset =
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Exception Model
233
Interrupts and Events