Cortex-M3 Processor Registers - Texas Instruments SimpleLink CC2620 Technical Reference Manual

www.ti.com
2.7

Cortex-M3 Processor Registers

2.7.1 CPU_DWT Registers
Table 2-26 lists the memory-mapped registers for the CPU_DWT. All register offset addresses not listed in
Table 2-26 must be considered as reserved locations and the register contents must not be modified.
Offset Acronym
0h CTRL
4h CYCCNT
8h CPICNT
Ch EXCCNT
10h SLEEPCNT
14h LSUCNT
18h FOLDCNT
1Ch PCSR
20h COMP0
24h MASK0
28h FUNCTION0
30h COMP1
34h MASK1
38h FUNCTION1
40h COMP2
44h MASK2
48h FUNCTION2
50h COMP3
54h MASK3
58h FUNCTION3
SWCU117C – February 2015 – Revised September 2015
Submit Documentation Feedback
Table 2-26. CPU_DWT Registers
Register Name
Control
Current PC Sampler Cycle Count
CPI Count
Exception Overhead Count
Sleep Count
LSU Count
Fold Count
Program Counter Sample
Comparator 0
Mask 0
Function 0
Comparator 1
Mask 1
Function 1
Comparator 2
Mask 2
Function 2
Comparator 3
Mask 3
Function 3
Copyright © 2015, Texas Instruments Incorporated
Cortex-M3 Processor Registers
Section
Section 2.7.1.1
Section 2.7.1.2
Section 2.7.1.3
Section 2.7.1.4
Section 2.7.1.5
Section 2.7.1.6
Section 2.7.1.7
Section 2.7.1.8
Section 2.7.1.9
Section 2.7.1.10
Section 2.7.1.11
Section 2.7.1.12
Section 2.7.1.13
Section 2.7.1.14
Section 2.7.1.15
Section 2.7.1.16
Section 2.7.1.17
Section 2.7.1.18
Section 2.7.1.19
Section 2.7.1.20
51