Texas Instruments SimpleLink CC2620 Technical Reference Manual page 429

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6.1.6.1.1 Clock Loss Detection
When the clock loss feature is enabled with the DDI_0_OSC:CTL0.CLK_LOSS_EN and the
AON_SYSCTL:RESETCTL.CLK_LOSS_EN registers, a detected loss of SCLK_LF results in a system
reset. After recovery, the AON_SYSCTL:RESETCTL.RESET_SRC register shows clock loss as the
source of reset.
NOTE: The application must set both DDI_0_OSC:CTL0.CLK_LOSS_EN and the
AON_SYSCTL:RESETCTL.CLK_LOSS_EN in order to enable Clock Loss Detection, it is not
enabled after boot.
6.1.6.1.2 Software-initiated System Reset
Writing to the AON_SYSCTL:RESETCTL.SYSRESET register results in a system reset. After recovery,
the AON_SYSCTL:RESETCTL.RESET_SRC register shows SYSRESET as the source of reset.
6.1.6.1.3 Warm Reset Converted to System Reset
Warm reset can be programmed with the PRCM:WARMRESET.WR_TO_PINRESET register to result in a
system reset when any warm reset source is triggered (see
NOTE: TI strongly recommends enabling the Warm Reset Converted to System Reset feature.
6.1.6.2 Warm Reset
A reset that results in a reset of the MCU_VD and the system CPU bus part of AUX_PD, is defined as a
warm reset. A warm reset leaves all analog configurations unchanged, while the system CPU and all other
digital modules in MCU_VD are reset.
The following sources initiate a warm reset generation:
• The CPU_SCS:AIRCR.SYSRESETREQ register
• System CPU LOCKUP
• Watchdog time-out
When a warm reset source is triggered, MCU_VD is reset through a controlled sequence, returning
MCU_VD to the same state as when finishing a boot from system reset.
The PRCM:WARMRESET register has readable bits that indicate if the MCU_VD was reset due to a
system CPU LOCKUP event or a watchdog time-out.
6.1.6.3 Software-Initiated Reset of MCU_VD
A feature to request a reset of MCU_VD is available. When writing the PRCM:SWRESET.MCU register,
AON_WUC does a controlled reset sequence of MCU_VD. This reset also clears the PRCM and other
logic in MCU_AON.
6.1.6.4 Reset of the MCU_VD Power Domains and Modules
Reset of logic in power domains are hardware controlled. A module without retention is reset when the
encapsulating power domain is power cycled. A module with retention resets when MCU_VD is power
cycled or reset.
6.1.6.5 Reset of AON_VD
AON_VD is reset by a system reset. See
SWCU117C – February 2015 – Revised September 2015
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Section 6.1.6.1, System Resets, for details.
Copyright © 2015, Texas Instruments Incorporated
Section 6.1.6.2, Warm Reset).
Power, Reset, and Clock Management
Introduction
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