Texas Instruments SimpleLink CC2620 Technical Reference Manual page 209

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2.7.5.2 CSPSR Register (Offset = 4h) [reset = 1h]
CSPSR is shown in
Current Sync Port Size
This register has the same format as SSPSR but only one bit can be set, and all others must be zero.
Writing values with more than one bit set, or setting a bit that is not indicated as supported can cause
Unpredictable behavior. On reset this defaults to the smallest possible port size, 1 bit.
31 30
23 22
15 14
7 6
RESERVED
Bit Field
31-4 RESERVED
3 FOUR
2 THREE
1 TWO
0 ONE
SWCU117C – February 2015 – Revised September 2015
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Figure 2-132 and described in
Figure 2-132. CSPSR Register
29 28
21 20
13 12
5 4
R/W-0h
Table 2-159. CSPSR Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 1h
Copyright © 2015, Texas Instruments Incorporated
Table 2-159.
27
RESERVED
R/W-0h
19
RESERVED
R/W-0h
11
RESERVED
R/W-0h
3
FOUR THREE
R/W-0h R/W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
4-bit port enable
Writing values with more than one bit set in CSPSR, or setting a bit
that is not indicated as supported in SSPSR can cause
Unpredictable behavior.
3-bit port enable
Writing values with more than one bit set in CSPSR, or setting a bit
that is not indicated as supported in SSPSR can cause
Unpredictable behavior.
2-bit port enable
Writing values with more than one bit set in CSPSR, or setting a bit
that is not indicated as supported in SSPSR can cause
Unpredictable behavior.
1-bit port enable
Writing values with more than one bit set in CSPSR, or setting a bit
that is not indicated as supported in SSPSR can cause
Unpredictable behavior.
Cortex-M3 Processor Registers
26 25
18 17
10 9
2 1
TWO
R/W-0h
24
16
8
0
ONE
R/W-1h
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