Texas Instruments SimpleLink CC2620 Technical Reference Manual page 671

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7.8.2.1 STAT Register (Offset = 0h) [reset = 0h]
STAT is shown in
Status
Displays current VIMS mode and line buffer status.
31 30
23 22
15 14
7 6
RESERVED
R-0h
Bit Field
31–6 RESERVED
5 IDCODE_LB_DIS
4 SYSBUS_LB_DIS
3 MODE_CHANGING
2 INV
1–0 MODE
SWCU117C – February 2015 – Revised September 2015
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Figure 7-133 and described in
Figure 7-133. STAT Register
29 28
21 20
13 12
5 4
IDCODE_LB_D SYSBUS_LB_D
IS IS
R-0h R-0h
Table 7-128. STAT Register Field Descriptions
Type Reset
R 0h
R 0h
R 0h
R 0h
R 0h
R 0h
Copyright © 2015, Texas Instruments Incorporated
Table 7-128.
27
RESERVED
R-0h
19
RESERVED
R-0h
11
RESERVED
R-0h
3
MODE_CHAN INV
GING
R-0h R-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Icode/Dcode flash line buffer status
0: Enabled or in transition to disabled
1: Disabled and flushed
Sysbus flash line buffer control
0: Enabled or in transition to disabled
1: Disabled and flushed
VIMS mode change status
0: VIMS is in the mode defined by MODE
1: VIMS is in the process of changing to the mode given in
CTL.MODE
This bit is set when invalidation of the cache memory is active or
ongoing
Current VIMS mode
0h = GPRAM : VIMS GPRAM mode
1h = CACHE : VIMS Cache mode
2h = VIMS Split Cache mode
3h = VIMS Off mode
Versatile Instruction Memory System (VIMS)
VIMS Registers
26 25
18 17
10 9
2 1
MODE
R-0h
24
16
8
0
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