Texas Instruments SimpleLink CC2620 Technical Reference Manual page 807

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10.1.4.3.1 Internal Operation
The DMAC operates with the AHB master adapter that has two ports. One port is an external AHB port
used to perform read and write operations to the external AHB subsystem. This port can address the
complete 32-bit address range. The second port is an internal TCM port (master TCM) used to perform
read and write operations to the internal modules of the crypto core AES engine and key store.
Assignment of the internal modules for DMA operation must be selected in the master control module (see
to Section 10.1.4.4.1.1, Algorithm Select); therefore, an internal address is not needed in the DMAC.
The data path from the TCM port of the AHB master module to the internal modules is located outside of
the DMAC. The DMAC only observes the number of transferred words to determine when the requested
DMA operation is finished for the corresponding channel.
The key store is a 32-bit block of memory with a depth of 32 words, surrounded by control logic. When the
AES module is configured to write keys to this key-store module through DMA, the key store internally
manages access to the key store RAM based on its register settings (including generation of the key store
RAM addresses). The AES module supports only DMA write operations to the key store.
The AES engine has a 32-bit write interface for input data to be encrypted or decrypted, and a 32-bit read
interface for result data and tag. The write interface of the AES module collects 32-bit data into a 128-bit
input block (AES block size). When a full block is received, the AES calculation for the received block is
started. When receiving the last word of the last block, the DMAC and master controller generate a "data
done" signal to the crypto engine. The mode, message length, and optional parameters are programmed
using the target interface.
On the TCM side, the key store module immediately accepts all data without delay cycles, while the crypto
modules operate on a data block boundary. On the TCM side, the key-store module immediately accepts
all data without delay cycles, while the crypto module operates on a data block boundary (the processing
of which takes a number of clock cycles). Special handshake signals are used between the DMAC and
crypto modules:
• A data input request is sent to the DMA inbound channel (channel 0) when the crypto module can
accept the next data block.
• A data output request is sent to the DMA output channel (channel 1) when the crypto module has the
next block of data or tag available, after processing or hash module has a digest available.
• Both channels send an acknowledge when the DMA operation starts, channel transfer completes,
when a block has been transmitted and the channel transfer completes, or when all data is transmitted.
10.1.4.3.2 Supported DMA Operations
With each data request from the crypto engine, the DMAC requests a transfer from the AHB master. The
transfer size is at most the block size of the corresponding algorithm. This block size depends on the
selected algorithm in the master control module.
Table 10-2 provides a summary of the supported DMAC operations. The module refers to the selected
module in the master control module. TAG enable indicates whether the TAG bit is set in the master
control configuration register.
Incoming Data Stream (for Channel 0)
Module
Key store External memory location
RAM (Authentication data only)
Crypto External memory location
(1)
TAG is transferred through the slave interface or transferred with a separate DMA.
(2)
Data is transferred through another DMA, that has been executed before.
SWCU117C – February 2015 – Revised September 2015
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Table 10-2. Supported DMAC Operations
Source Destination
Key store RAM
AES
AES
(2) (2)
See See
Copyright © 2015, Texas Instruments Incorporated
AES Cryptoprocessor Overview
Outcoming Data Stream (for Channel 1)
Source
–
(1)
See
AES External memory location
AES (TAG enabled) External memory location
Destination
–
(1)
See
807
Cryptography