Texas Instruments SimpleLink CC2620 Technical Reference Manual page 806

AES Cryptoprocessor Overview
The required parameters for proper functioning of the AHB master interface port are defined in the
DMABUSCFG register. The default configuration of this register configures fixed-length transfers and a
maximum burst size of 4 bytes. As a result, only nonsequential single transfers are performed on the AHB
bus.
The DMASTAT and DMAPORTERR registers provide the actual state of each DMA channel and individual
AHB port errors. A port error aborts operations on all serviced channels and prevents further transfers
using that port, until the error is cleared by writing to the DMASWRESET register.
If the address and lengths are 32-bit aligned, the master does only NONSEQ- and SINGLE-type transfers
with a size of 4 bytes.
The DMAC splits channel DMA operation into small DMA transfers. The size of small DMA transfers is
determined by the target internal module, and equals the block size of the cryptographic operation.
The DMAC has the following features:
• Two channels (one inbound and one outbound) that can be enabled at the same time
• A maximum size of the DMA operation, controlled by a 16-bit long register
• An arbiter to schedule channel accesses to the external AHB port
• Functionality to capture external bus errors
The DMAC consists of two DMA channels with programmable priority: one is programmable to move input
data and keys from the external memory to the AES module, and another is programmable to move result
data from the AES module to the external memory. Access to the channels of the AHB master port is
handled by the arbiter module.
Channel control registers are used for channel enabling and priority selection. When a channel is
disabled, it becomes inactive only when all ongoing requests are finished.
NOTE: All the channel control registers (DMACHxCTL, DMACHxEXTADDR, and DMACHxLEN)
must be programmed by the host to start a new DMA operation.
The DMAC transfers data between a source address and destination address. Starting at a nonword-
aligned boundary, byte transfers are generated until a word boundary is reached. From then onward, word
transfers are generated as long as data is available. If the transfer does not finish on word-aligned
address, the remaining transfers are again byte transfers.
NOTE: No halfword transfers are generated.
When the AHB_MST1_INCR_EN bit is set to 1, defined-length bursts and single transfers are generated
by default. The maximum size depends on the programmed burst size.
The DMAC registers are mapped to the external register map. To start the operation, the host must
program the mode of the DMAC and parameters of the operation. These parameters involve direction
(read, write, or read-and-write), length (1 to 65535 bytes), external source address (for reading), and
external destination address (for writing). For details of the registers, refer to
Registers.
NOTE: The internal destination is programmed using a dedicated algorithm selection register in
master control module. The burst size is provided to the DMAC based on the setting of that
register.
806
Cryptography
Copyright © 2015, Texas Instruments Incorporated
Section 10.2.1, CRYPTO
SWCU117C – February 2015 – Revised September 2015
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