Texas Instruments SimpleLink CC2620 Technical Reference Manual page 74

Cortex-M3 Processor Registers
2.7.1.19 MASK3 Register (Offset = 54h) [reset = X]
MASK3 is shown in
Mask 3
Use the DWT Mask Registers 3 to apply a mask to data addresses when matching against COMP3.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Field
31-4 RESERVED
3-0 MASK
74
Figure 2-22 and described in
Figure 2-22. MASK3 Register
RESERVED
R/W-0h
Table 2-45. MASK3 Register Field Descriptions
Type Reset
R/W 0h
R/W X
Copyright © 2015, Texas Instruments Incorporated
Table 2-45.
9
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Mask on data address when matching against COMP3. This is the
size of the ignore mask. That is, DWT matching is performed
as:(ADDR ANDed with (0xFFFF left bit-shifted by MASK)) ==
COMP3. However, the actual comparison is slightly more complex to
enable matching an address wherever it appears on a bus. So, if
COMP3 is 3, this matches a word access of 0, because 3 would be
within the word.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
8 7 6 5 4 3 2 1
MASK
R/W-X
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