Texas Instruments SimpleLink CC2620 Technical Reference Manual page 205

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Table 2-155. DEMCR Register Field Descriptions (continued)
Bit Field
16 MON_EN
15-11 RESERVED
10 VC_HARDERR
9 VC_INTERR
8 VC_BUSERR
7 VC_STATERR
6 VC_CHKERR
5 VC_NOCPERR
4 VC_MMERR
3-1 RESERVED
0 VC_CORERESET
SWCU117C – February 2015 – Revised September 2015
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Type Reset Description
R/W 0h Enable the debug monitor.
When enabled, the System handler priority register controls its
priority level. If disabled, then all debug events go to Hard fault.
DHCSR.C_DEBUGEN overrides this bit. Vector catching is semi-
synchronous. When a matching event is seen, a Halt is requested.
Because the processor can only halt on an instruction boundary, it
must wait until the next instruction boundary. As a result, it stops on
the first instruction of the exception handler. However, two special
cases exist when a vector catch has triggered: 1. If a fault is taken
during vectoring, vector read or stack push error, the halt occurs on
the corresponding fault handler, for the vector error or stack push. 2.
If a late arriving interrupt comes in during vectoring, it is not taken.
That is, an implementation that supports the late arrival optimization
must suppress it in this case.
R/W 0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
R/W 0h
Debug trap on Hard Fault. Ignored when DHCSR.C_DEBUGEN is
cleared.
R/W 0h
Debug trap on a fault occurring during an exception entry or return
sequence. Ignored when DHCSR.C_DEBUGEN is cleared.
R/W 0h
Debug Trap on normal Bus error. Ignored when
DHCSR.C_DEBUGEN is cleared.
R/W 0h
Debug trap on Usage Fault state errors. Ignored when
DHCSR.C_DEBUGEN is cleared.
R/W 0h
Debug trap on Usage Fault enabled checking errors. Ignored when
DHCSR.C_DEBUGEN is cleared.
R/W 0h
Debug trap on a UsageFault access to a Coprocessor. Ignored when
DHCSR.C_DEBUGEN is cleared.
R/W 0h
Debug trap on Memory Management faults. Ignored when
DHCSR.C_DEBUGEN is cleared.
R/W 0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
R/W 0h
Reset Vector Catch. Halt running system if Core reset occurs.
Ignored when DHCSR.C_DEBUGEN is cleared.
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Cortex-M3 Processor Registers
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