Tpiu - Texas Instruments SimpleLink CC2620 Technical Reference Manual

Functional Description
3.2.4 ITM
The ITM is an application-driven trace source that supports printf() style debugging to trace operating
system and application events, and generates diagnostic system information. The ITM generates trace
information as packets. If multiple sources generate packets at the same time, the ITM arbitrates the order
in which packets are output. These sources in decreasing order of priority are the following:
• Software trace: Software can write directly to ITM stimulus registers to generate packets.
• Hardware trace: The DWT generates these packets, and the ITM outputs the packets.
• Time stamping: Timestamps are generated relative to packets. The ITM contains a 21-bit counter to
generate the timestamp. The Cortex-M3 clock or the bit-clock rate of the serial wire viewer (SWV)
output clocks the counter.
NOTE: ITM registers are fully accessible in privileged mode. In user mode, all registers can be
read, but only the Stimulus Registers and Trace Enable Registers can be written, and only
when the corresponding Trace Privilege Register bit is set. Invalid user mode writes to the
ITM registers are discarded.
3.2.5 FPB
The FPB implements hardware breakpoints and patches code and data from the Code space to the
System space.
A full FPB unit contains:
• Two literal comparators match against literal loads from the Code space, and remap to a
corresponding area in the System space.
• Six instruction comparators for matching against instruction fetches from the Code space, and remaps
to a corresponding area in the System space. Alternatively, the comparators can be individually
configured to return a Breakpoint (BKPT) instruction to the processor core on a match for hardware
breakpoint capability.
A reduced FPB unit contains:
• Two instruction comparators that can be configured individually to return a BKPT instruction to the
processor on a match, and to provide hardware breakpoint capability
The FPB contains a global enable and individual enables for the eight comparators. If the comparison for
an entry matches, the address is either:
• Remapped to the address set in the remap register plus an offset corresponding to the matched
comparator
or
• Remapped to a BKPT instruction if that feature is enabled
The comparison happens dynamically, but the result of the comparison occurs too late to stop the original
instruction fetch or literal load taking place from the Code space. The processor ignores this transaction,
however, and only the remapped transaction is used.
If the FPB supports only two breakpoints, then only comparators 0 and 1 are used, and the FPB does not
support flash patching.

3.2.6 TPIU

The Cortex-M3 TPIU acts as a bridge between the on-chip trace data from the embedded trace macrocell
(ETM) and the instrumentation trace macrocell (ITM), with separate IDs, to a data stream. The TPIU
encapsulates IDs where required, and the data stream is then captured by a trace port analyzer (TPA).
There are two configurations of the TPIU:
• A configuration that supports ITM debug trace
• A configuration that supports both ITM and ETM debug trace
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Cortex-M3 Peripherals
Copyright © 2015, Texas Instruments Incorporated
SWCU117C – February 2015 – Revised September 2015
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