Texas Instruments SimpleLink CC2620 Technical Reference Manual page 121

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2.7.3.33 TER Register (Offset = E00h) [reset = 0h]
TER is shown in Figure 2-66
Trace Enable
Use the Trace Enable Register to generate trace data by writing to the corresponding stimulus port. Note:
Privileged writes are accepted to this register if TCR.ITMENA is set. User writes are accepted to this
register if TCR.ITMENA is set and the appropriate privilege mask is cleared. Privileged access to the
stimulus ports enables an RTOS kernel to ensure instrumentation slots or bandwidth as required.
31 30
STIMENA31 STIMENA30
R/W-0h R/W-0h
23 22
STIMENA23 STIMENA22
R/W-0h R/W-0h
15 14
STIMENA15 STIMENA14
R/W-0h R/W-0h
7 6
STIMENA7 STIMENA6
R/W-0h R/W-0h
Bit Field
31 STIMENA31
30 STIMENA30
29 STIMENA29
28 STIMENA28
27 STIMENA27
26 STIMENA26
25 STIMENA25
24 STIMENA24
23 STIMENA23
22 STIMENA22
21 STIMENA21
20 STIMENA20
19 STIMENA19
18 STIMENA18
17 STIMENA17
16 STIMENA16
15 STIMENA15
14 STIMENA14
13 STIMENA13
12 STIMENA12
11 STIMENA11
10 STIMENA10
SWCU117C – February 2015 – Revised September 2015
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and described in Table
Figure 2-66. TER Register
29 28
STIMENA29 STIMENA28
R/W-0h R/W-0h
21 20
STIMENA21 STIMENA20
R/W-0h R/W-0h
13 12
STIMENA13 STIMENA12
R/W-0h R/W-0h
5 4
STIMENA5 STIMENA4
R/W-0h R/W-0h
Table 2-91. TER Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
2-91.
27 26
STIMENA27 STIMENA26
R/W-0h R/W-0h
19 18
STIMENA19 STIMENA18
R/W-0h R/W-0h
11 10
STIMENA11 STIMENA10
R/W-0h R/W-0h
3 2
STIMENA3 STIMENA2
R/W-0h R/W-0h
Description
Bit mask to enable tracing on ITM stimulus port 31.
Bit mask to enable tracing on ITM stimulus port 30.
Bit mask to enable tracing on ITM stimulus port 29.
Bit mask to enable tracing on ITM stimulus port 28.
Bit mask to enable tracing on ITM stimulus port 27.
Bit mask to enable tracing on ITM stimulus port 26.
Bit mask to enable tracing on ITM stimulus port 25.
Bit mask to enable tracing on ITM stimulus port 24.
Bit mask to enable tracing on ITM stimulus port 23.
Bit mask to enable tracing on ITM stimulus port 22.
Bit mask to enable tracing on ITM stimulus port 21.
Bit mask to enable tracing on ITM stimulus port 20.
Bit mask to enable tracing on ITM stimulus port 19.
Bit mask to enable tracing on ITM stimulus port 18.
Bit mask to enable tracing on ITM stimulus port 17.
Bit mask to enable tracing on ITM stimulus port 16.
Bit mask to enable tracing on ITM stimulus port 15.
Bit mask to enable tracing on ITM stimulus port 14.
Bit mask to enable tracing on ITM stimulus port 13.
Bit mask to enable tracing on ITM stimulus port 12.
Bit mask to enable tracing on ITM stimulus port 11.
Bit mask to enable tracing on ITM stimulus port 10.
Cortex-M3 Processor Registers
25 24
STIMENA25 STIMENA24
R/W-0h R/W-0h
17 16
STIMENA17 STIMENA16
R/W-0h R/W-0h
9 8
STIMENA9 STIMENA8
R/W-0h R/W-0h
1 0
STIMENA1 STIMENA0
R/W-0h R/W-0h
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