Texas Instruments SimpleLink CC2620 Technical Reference Manual page 44

Cortex-M3 Core Registers
2.5.2.18 Priority Mask Register (PRIMASK)
Address Offset
Physical Address
Description
The Priority Mask (PRIMASK) register prevents activation of all exceptions with programmable priority. Reset, nonmaskable interrupt (NMI),
and hard fault are the only exceptions with fixed priority. Exceptions must be disabled when they might impact the timing of critical tasks.
This register is accessible only in privileged mode. The MSR and MRS instructions are used to access the PRIMASK register, and the CPS
instruction may be used to change the value of the PRIMASK register. For more information on these instructions, see the Cortex-M3/M4F
Instruction Set Technical User's Manual (SPMU159). For more information on exception priority levels, see
Type
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits Field Name
31–1 RESERVED
0 PRIMASK
44
Table 2-21. Priority Mask Register (PRIMASK)
R/W
RESERVED
Description
Software must not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit must
be preserved across a read-modify-write operation.
Priority Mask
Value Description
1 Prevents the activation of all exceptions with configurable
priority
0 No effect
Copyright © 2015, Texas Instruments Incorporated
Reset
Instance
9
SWCU117C – February 2015 – Revised September 2015
www.ti.com
0x0000 0000
Section 4.1.2, Exception Types.
8 7 6 5 4 3 2 1
Type Reset
RO 0x0000 000
R/W 0
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