Texas Instruments SimpleLink CC2620 Technical Reference Manual page 124

Cortex-M3 Processor Registers
2.7.3.35 TCR Register (Offset = E80h) [reset = 0h]
TCR is shown in Figure 2-68
Trace Control
Use this register to configure and control ITM transfers. This register can only be written in privilege mode.
DWT is not enabled in the ITM block. However, DWT stimulus entry into the FIFO is controlled by
DWTENA. If DWT requires timestamping, the TSENA bit must be set.
31 30
23 22
BUSY
R/W-0h
15 14
7 6
RESERVED
R/W-0h
Bit Field
31-24 RESERVED
23 BUSY
22-16 ATBID
15-10 RESERVED
9-8 TSPRESCALE
7-5 RESERVED
4 SWOENA
3 DWTENA
2 SYNCENA
124
and described in Table
Figure 2-68. TCR Register
29 28
RESERVED
R/W-0h
21 20
13 12
RESERVED
R/W-0h
5 4
SWOENA
R/W-0h
Table 2-93. TCR Register Field Descriptions
Type Reset Description
R/W 0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
R/W 0h
Set when ITM events present and being drained.
R/W 0h
Trace Bus ID for CoreSight system. Optional identifier for multi-
source trace stream formatting. If multi-source trace is in use, this
field must be written with a non-zero value.
R/W 0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
R/W 0h
Timestamp prescaler
0h = No prescaling
1h = Divide by 4
2h = Divide by 16
3h = Divide by 64
R/W 0h
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
R/W 0h Enables asynchronous clocking of the timestamp counter (when
TSENA = 1). If TSENA = 0, writing this bit to 1 does not enable
asynchronous clocking of the timestamp counter.
0x0: Mode disabled. Timestamp counter uses system clock from the
core and counts continuously.
0x1: Timestamp counter uses lineout (data related) clock from TPIU
interface. The timestamp counter is held in reset while the output line
is idle.
R/W 0h
Enables the DWT stimulus (hardware event packet emission to the
TPIU from the DWT)
R/W 0h Enables synchronization packet transmission for a synchronous
TPIU.
CPU_DWT:CTRL.SYNCTAP must be configured for the correct
synchronization speed.
Copyright © 2015, Texas Instruments Incorporated
2-93.
27 26
19 18
ATBID
R/W-0h
11 10
3 2
DWTENA SYNCENA
R/W-0h R/W-0h
SWCU117C – February 2015 – Revised September 2015
www.ti.com
25 24
17 16
9 8
TSPRESCALE
R/W-0h
1 0
TSENA ITMENA
R/W-0h R/W-0h
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