VIMS Registers
7.8.1.8
EFUSEADDR Register (Offset = 1004h) [reset = 0h]
EFUSEADDR is shown in
Internal. Only to be used through TI provided API.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Bit
Field
31-16
RESERVED
15-11
BLOCK
10-0
ROW
554
Versatile Instruction Memory System (VIMS)
Figure 7-17
and described in
Figure 7-17. EFUSEADDR Register
R-0h
Table 7-11. EFUSEADDR Register Field Descriptions
Type
Reset
R
0h
R/W
0h
R/W
0h
Copyright © 2015, Texas Instruments Incorporated
Table
7-11.
9
BLOCK
R/W-0h
Description
Internal. Only to be used through TI provided API.
Internal. Only to be used through TI provided API.
Internal. Only to be used through TI provided API.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
8
7
6
5
4
3
2
1
ROW
R/W-0h
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