www.ti.com
7.8.1.85 FSM_SAV_ERA_PUL Register (Offset = 2254h) [reset = 0h]
FSM_SAV_ERA_PUL is shown in
Internal. Only to be used through TI provided API.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit
Field
31-12
RESERVED
11-0
SAV_ERA_PUL
SWCU117C – February 2015 – Revised September 2015
Submit Documentation Feedback
Figure 7-94
Figure 7-94. FSM_SAV_ERA_PUL Register
RESERVED
R-0h
Table 7-88. FSM_SAV_ERA_PUL Register Field Descriptions
Type
Reset
R
0h
R
0h
Copyright © 2015, Texas Instruments Incorporated
and described in
Table
7-88.
Description
Internal. Only to be used through TI provided API.
Internal. Only to be used through TI provided API.
Versatile Instruction Memory System (VIMS)
VIMS Registers
9
8
7
6
5
4
3
2
SAV_ERA_PUL
R-0h
1
0
631