Texas Instruments SimpleLink CC2620 Technical Reference Manual page 507

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6.2.4.32 I2SCLKCTL Register (Offset = D0h) [reset = 0h]
I2SCLKCTL is shown in
I2S Clock Control
31 30
23 22
15 14
7 6
RESERVED
Bit Field
31-4 RESERVED
3 SMPL_ON_POSEDGE
2-1 WCLK_PHASE
0 EN
SWCU117C – February 2015 – Revised September 2015
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Figure 6-71 and described in
Figure 6-71. I2SCLKCTL Register
29 28
21 20
13 12
5 4
R-0h
Table 6-76. I2SCLKCTL Register Field Descriptions
Type Reset
R 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 6-76.
27
RESERVED
R-0h
19
RESERVED
R-0h
11
RESERVED
R-0h
3
SMPL_ON_PO
SEDGE
R/W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
On the I2S serial interface, data and WCLK is sampled and clocked
out on opposite edges of BCLK.
0 - data and WCLK are sampled on the negative edge and clocked
out on the positive edge.
1 - data and WCLK are sampled on the positive edge and clocked
out on the negative edge.
For changes to take effect, CLKLOADCTL.LOAD needs to be written
Decides how the WCLK division ratio is calculated and used to
generate different duty cycles (See I2SWCLKDIV.WDIV).
0: Single phase
1: Dual phase
2: User Defined
3: Reserved/Undefined
For changes to take effect, CLKLOADCTL.LOAD needs to be written
0: MCLK, BCLK and **WCLK** will be static low
1: Enables the generation of MCLK, BCLK and WCLK
For changes to take effect, CLKLOADCTL.LOAD needs to be written
Power, Reset, and Clock Management
PRCM Registers
26 25
18 17
10 9
2 1
WCLK_PHASE
R/W-0h
24
16
8
0
EN
R/W-0h
507