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7.8.1.73 FSM_PE_OSU Register (Offset = 2210h) [reset = 0h]
FSM_PE_OSU is shown in
Internal. Only to be used through TI provided API.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RESERVED
Bit
Field
31-16
RESERVED
15-8
PGM_OSU
7-0
ERA_OSU
SWCU117C – February 2015 – Revised September 2015
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Figure 7-82
and described in
Figure 7-82. FSM_PE_OSU Register
R-0h
Table 7-76. FSM_PE_OSU Register Field Descriptions
Type
Reset
R
0h
R/W
0h
R/W
0h
Copyright © 2015, Texas Instruments Incorporated
Table
7-76.
9
PGM_OSU
R/W-0h
Description
Internal. Only to be used through TI provided API.
Internal. Only to be used through TI provided API.
Internal. Only to be used through TI provided API.
Versatile Instruction Memory System (VIMS)
VIMS Registers
8
7
6
5
4
3
2
1
ERA_OSU
R/W-0h
0
619