Texas Instruments SimpleLink CC2620 Technical Reference Manual page 72

Cortex-M3 Processor Registers
Table 2-43. FUNCTION2 Register Field Descriptions (continued)
Bit Field
3-0 FUNCTION
72
Type Reset Description
R/W 0h Function settings.
0x0: Disabled
0x1: EMITRANGE = 0, sample and emit PC through ITM.
EMITRANGE = 1, emit address offset through ITM
0x2: EMITRANGE = 0, emit data through ITM on read and write.
EMITRANGE = 1, emit data and address offset through ITM on read
or write.
0x3: EMITRANGE = 0, sample PC and data value through ITM on
read or write. EMITRANGE = 1, emit address offset and data value
through ITM on read or write.
0x4: Watchpoint on PC match.
0x5: Watchpoint on read.
0x6: Watchpoint on write.
0x7: Watchpoint on read or write.
0x8: ETM trigger on PC match
0x9: ETM trigger on read
0xA: ETM trigger on write
0xB: ETM trigger on read or write
0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE
= 1, sample Daddr (lower 16 bits) for read transfers
0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE
= 1, sample Daddr (lower 16 bits) for write transfers
0xE: EMITRANGE = 0, sample PC + data for read transfers.
EMITRANGE = 1, sample Daddr (lower 16 bits) + data for read
transfers
0xF: EMITRANGE = 0, sample PC + data for write transfers.
EMITRANGE = 1, sample Daddr (lower 16 bits) + data for write
transfers
Note 1: If the ETM is not fitted, then ETM trigger is not possible.
Note 2: Data value is only sampled for accesses that do not fault
(MPU or bus fault). The PC is sampled irrespective of any faults. The
PC is only sampled for the first address of a burst.
Note 3: PC match is not recommended for watchpoints because it
stops after the instruction. It mainly guards and triggers the ETM.
Copyright © 2015, Texas Instruments Incorporated
SWCU117C – February 2015 – Revised September 2015
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