Texas Instruments SimpleLink CC2620 Technical Reference Manual page 504

PRCM Registers
6.2.4.29 CPUCLKDIV Register (Offset = B8h) [reset = 0h]
CPUCLKDIV is shown in
Internal. Only to be used through TI provided API.
31 30
23 22
15 14
7 6
Bit Field
31-1 RESERVED
0 RATIO
504
Power, Reset, and Clock Management
Figure 6-68 and described in
Figure 6-68. CPUCLKDIV Register
29 28
RESERVED
R-0h
21 20
RESERVED
R-0h
13 12
RESERVED
R-0h
5 4
RESERVED
R-0h
Table 6-73. CPUCLKDIV Register Field Descriptions
Type Reset
R 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 6-73.
27 26
19 18
11 10
3 2
Description
Internal. Only to be used through TI provided API.
Internal. Only to be used through TI provided API.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
25 24
17 16
9 8
1 0
RATIO
R/W-0h
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