Texas Instruments SimpleLink CC2620 Technical Reference Manual page 500

PRCM Registers
6.2.4.25 SSICLKGDS Register (Offset = 80h) [reset = 0h]
SSICLKGDS is shown in
SSI Clock Gate For Deep Sleep Mode
31 30 29 28
15 14 13 12
Bit Field
31-2 RESERVED
1-0 CLK_EN
500
Power, Reset, and Clock Management
Figure 6-64 and described in
Figure 6-64. SSICLKGDS Register
27 26 25 24
RESERVED
R-0h
11 10 9 8
RESERVED
R-0h
Table 6-69. SSICLKGDS Register Field Descriptions
Type Reset
R 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 6-69.
23 22 21 20
7 6 5 4
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written
1h = Enable clock for SSI0
2h = Enable clock for SSI1
SWCU117C – February 2015 – Revised September 2015
www.ti.com
19 18 17 16
3 2 1 0
CLK_EN
R/W-0h
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