Texas Instruments SimpleLink CC2620 Technical Reference Manual page 152

Cortex-M3 Processor Registers
2.7.4.15 NVIC_IABR0 Register (Offset = 300h) [reset = 0h]
NVIC_IABR0 is shown in
Irq 0 to 31 Active Bit
This register is used to determine which interrupts are active. Each flag in the register corresponds to one
interrupt.
31 30
ACTIVE31 ACTIVE30
R-0h R-0h
23 22
ACTIVE23 ACTIVE22
R-0h R-0h
15 14
ACTIVE15 ACTIVE14
R-0h R-0h
7 6
ACTIVE7 ACTIVE6
R-0h R-0h
Bit Field
31 ACTIVE31
30 ACTIVE30
29 ACTIVE29
28 ACTIVE28
27 ACTIVE27
26 ACTIVE26
25 ACTIVE25
24 ACTIVE24
23 ACTIVE23
22 ACTIVE22
21 ACTIVE21
152
Figure 2-85 and described in
Figure 2-85. NVIC_IABR0 Register
29 28
ACTIVE29 ACTIVE28
R-0h R-0h
21 20
ACTIVE21 ACTIVE20
R-0h R-0h
13 12
ACTIVE13 ACTIVE12
R-0h R-0h
5 4
ACTIVE5 ACTIVE4
R-0h R-0h
Table 2-111. NVIC_IABR0 Register Field Descriptions
Type Reset
R 0h
R 0h
R 0h
R 0h
R 0h
R 0h
R 0h
R 0h
R 0h
R 0h
R 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-111.
27 26
ACTIVE27 ACTIVE26
R-0h R-0h
19 18
ACTIVE19 ACTIVE18
R-0h R-0h
11 10
ACTIVE11 ACTIVE10
R-0h R-0h
3 2
ACTIVE3 ACTIVE2
R-0h R-0h
Description
Reading 0 from this bit implies that interrupt line 31 is not active.
Reading 1 from this bit implies that the interrupt line 31 is active (See
EVENT:CPUIRQSEL31.EV for details).
Reading 0 from this bit implies that interrupt line 30 is not active.
Reading 1 from this bit implies that the interrupt line 30 is active (See
EVENT:CPUIRQSEL30.EV for details).
Reading 0 from this bit implies that interrupt line 29 is not active.
Reading 1 from this bit implies that the interrupt line 29 is active (See
EVENT:CPUIRQSEL29.EV for details).
Reading 0 from this bit implies that interrupt line 28 is not active.
Reading 1 from this bit implies that the interrupt line 28 is active (See
EVENT:CPUIRQSEL28.EV for details).
Reading 0 from this bit implies that interrupt line 27 is not active.
Reading 1 from this bit implies that the interrupt line 27 is active (See
EVENT:CPUIRQSEL27.EV for details).
Reading 0 from this bit implies that interrupt line 26 is not active.
Reading 1 from this bit implies that the interrupt line 26 is active (See
EVENT:CPUIRQSEL26.EV for details).
Reading 0 from this bit implies that interrupt line 25 is not active.
Reading 1 from this bit implies that the interrupt line 25 is active (See
EVENT:CPUIRQSEL25.EV for details).
Reading 0 from this bit implies that interrupt line 24 is not active.
Reading 1 from this bit implies that the interrupt line 24 is active (See
EVENT:CPUIRQSEL24.EV for details).
Reading 0 from this bit implies that interrupt line 23 is not active.
Reading 1 from this bit implies that the interrupt line 23 is active (See
EVENT:CPUIRQSEL23.EV for details).
Reading 0 from this bit implies that interrupt line 22 is not active.
Reading 1 from this bit implies that the interrupt line 22 is active (See
EVENT:CPUIRQSEL22.EV for details).
Reading 0 from this bit implies that interrupt line 21 is not active.
Reading 1 from this bit implies that the interrupt line 21 is active (See
EVENT:CPUIRQSEL21.EV for details).
SWCU117C – February 2015 – Revised September 2015
www.ti.com
25 24
ACTIVE25 ACTIVE24
R-0h R-0h
17 16
ACTIVE17 ACTIVE16
R-0h R-0h
9 8
ACTIVE9 ACTIVE8
R-0h R-0h
1 0
ACTIVE1 ACTIVE0
R-0h R-0h
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