On-Chip Memory - Texas Instruments SimpleLink CC2620 Technical Reference Manual

Functional Overview
1.3.1.2 System Timer (SysTick)
ARM Cortex-M3 includes an integrated system timer (SysTick). SysTick provides a simple, 24-bit, clear-
on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used
in several different ways; for example:
• An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine
• A high-speed alarm timer using system clock 11
• A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and
the dynamic range of the counter
• A simple counter used to measure time to completion and time used
• An internal clock-source control based on missing or meeting durations
1.3.1.3 Nested Vector Interrupt Controller (NVIC)
The CC26xx and CC13xx device controller includes the ARM NVIC. The NVIC and Cortex-M3 prioritize
and handle all exceptions in handler mode. The processor state is automatically stored to the stack on an
exception and automatically restored from the stack at the end of the interrupt service routine (ISR). The
interrupt vector is fetched in parallel to state saving, thus enabling efficient interrupt entry. The processor
supports tail-chaining, that is, back-to-back interrupts can be performed without the overhead of state
saving and restoration. Software can set eight priority levels on seven exceptions (system handlers) and
can set CC26xx and CC13xx device interrupts.
Features of the NVIC are as follows:
• Deterministic, fast interrupt processing
– Always 12 cycles, or just 6 cycles with tail-chaining
• External nonmaskable interrupt (NMI) signal available for immediate execution of NMI handler for
safety-critical applications
• Dynamically reprioritizable interrupts
• Exceptional interrupt handling through hardware implementation of required register manipulations
1.3.1.4 System Control Block
The system control block (SCB) provides system implementation information and system control
(configuration, control, and reporting of system exceptions).

1.3.2 On-chip Memory

The following subsections describe the on-chip memory modules.
1.3.2.1 SRAM
The CC26xx and CC13xx devices provide low leakage on-chip SRAM with optional retention in all power
modes. Retention can be configured per block, and the device contains two blocks of 6KB and two blocks
of 4KB. Additionally, the flash cache RAM can be reconfigured to operate as normal system RAM.
Because read-modify-write (RMW) operations are very time consuming, ARM has introduced bit-banding
technology in the Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory
map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic
operation.
Data can be transferred to and from the SRAM using the micro DMA (µDMA) controller.
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Architectural Overview
Copyright © 2015, Texas Instruments Incorporated
SWCU117C – February 2015 – Revised September 2015
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