Texas Instruments SimpleLink CC2620 Technical Reference Manual page 787

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9.2.1.66 CONFIG_MISC_ADC Register (Offset = 380h) [reset = X]
CONFIG_MISC_ADC is shown in
Configuration of IFADC in Divide-by-2 Mode
31 30
23 22
15 14
7 6
QUANTCTLTHRES
R-5h
Bit Field
31-18 RESERVED
17 RSSITRIMCOMPLETE_N
16-9 RSSI_OFFSET
8-6 QUANTCTLTHRES
5-0 DACTRIM
SWCU117C – February 2015 – Revised September 2015
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Figure 9-88
Figure 9-88. CONFIG_MISC_ADC Register
29 28
RESERVED
21 20
RESERVED
R-3FFFh
13 12
RSSI_OFFSET
R-X
5 4
Table 9-90. CONFIG_MISC_ADC Register Field Descriptions
Type Reset
R 3FFFh
R X
R X
R 5h
R Dh
Copyright © 2015, Texas Instruments Incorporated
and described in Table 9-90.
27 26
R-3FFFh
19 18
11 10
3 2
DACTRIM
R-Dh
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Status of RSSI trim
0: Trimmed
1: Not trimmed
Default value holds trim value from production test.
Value for RSSI measured in production test.
Value is read by RF Core ROM FW during RF Core initialization.
Default value holds trim value from production test.
Trim value for ADI_0_RF:IFADCQUANT0.TH.
Value is read by RF Core ROM FW during RF Core initialization.
Trim value for ADI_0_RF:IFADCDAC.TRIM.
Value is read by RF Core ROM FW during RF Core initialization.
Factory Configuration (FCFG)
25 24
17 16
RSSITRIMCOM RSSI_OFFSET
PLETE_N
R-X R-X
9 8
QUANTCTLTH
RES
R-5h
1 0
787
Device Configuration