Texas Instruments SimpleLink CC2620 Technical Reference Manual page 482

PRCM Registers
6.2.4.7 VIMSCLKG Register (Offset = 30h) [reset = 3h]
VIMSCLKG is shown in
VIMS Clock Gate
31 30 29 28
15 14 13 12
Bit Field
31-2 RESERVED
1-0 CLK_EN
482
Power, Reset, and Clock Management
Figure 6-46 and described in
Figure 6-46. VIMSCLKG Register
27 26 25 24
RESERVED
R-0h
11 10 9 8
RESERVED
R-0h
Table 6-51. VIMSCLKG Register Field Descriptions
Type Reset
R 0h
R/W 3h
Copyright © 2015, Texas Instruments Incorporated
Table 6-51.
23 22 21 20
7 6 5 4
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
00: Disable clock
01: Disable clock when SYSBUS clock is disabled
11: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written
SWCU117C – February 2015 – Revised September 2015
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19 18 17 16
3 2 1 0
CLK_EN
R/W-3h
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