Texas Instruments SimpleLink CC2620 Technical Reference Manual page 446

PRCM Registers
6.2.1.14 STAT0 Register (Offset = 34h) [reset = 0h]
STAT0 is shown in
Status 0
This register contains status signals from OSC_DIG
31 30
SPARE31 SCLK_LF_SRC
R-0h
23 22
RESERVED RCOSC_HF_E
N
R-0h R-0h
15 14
XOSC_HF_EN RESERVED
R-0h R-0h
7 6
ADC_DATA_R
EADY
R-0h
Bit Field
31 SPARE31
30-29 SCLK_LF_SRC
28 SCLK_HF_SRC
27-23 RESERVED
22 RCOSC_HF_EN
21 RCOSC_LF_EN
20 XOSC_LF_EN
19 CLK_DCDC_RDY
18 CLK_DCDC_RDY_ACK
17 SCLK_HF_LOSS
16 SCLK_LF_LOSS
15 XOSC_HF_EN
14 RESERVED
13 XB_48M_CLK_EN
446
Power, Reset, and Clock Management
Figure 6-20 and described in
Figure 6-20. STAT0 Register
29 28
SCLK_HF_SR
C
R-0h R-0h
21 20
RCOSC_LF_E XOSC_LF_EN
N
R-0h R-0h
13 12
XB_48M_CLK_ RESERVED
EN
R-0h R-0h
5 4
Table 6-22. STAT0 Register Field Descriptions
Type Reset
R 0h
R 0h
R 0h
R 0h
R 0h
R 0h
R 0h
R 0h
R 0h
R 0h
R 0h
R 0h
R 0h
R 0h
Copyright © 2015, Texas Instruments Incorporated
Table 6-22.
27
19
CLK_DCDC_R CLK_DCDC_R SCLK_HF_LOS SCLK_LF_LOS
DY DY_ACK
R-0h R-0h
11
XOSC_HF_LP_ XOSC_HF_HP
BUF_EN _BUF_EN
R-0h R-0h
3
ADC_DATA
R-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Indicates source for the sclk_lf
0h = Low frequency clock derived from High Frequency RCOSC
1h = Low frequency clock derived from High Frequency XOSC
2h = Low frequency RCOSC
3h = Low frequency XOSC
Indicates source for the sclk_hf
0h = High frequency RCOSC clk
1h = High frequency XOSC
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
RCOSC_HF_EN
RCOSC_LF_EN
XOSC_LF_EN
CLK_DCDC_RDY
CLK_DCDC_RDY_ACK
Indicates sclk_hf is lost
Indicates sclk_lf is lost
Indicates that XOSC_HF is enabled.
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Indicates that the 48MHz clock from the DOUBLER is enabled.
It will be enabled if 24 or 48 MHz chrystal is used (enabled in
doulbler bypass for the 48MHz chrystal).
SWCU117C – February 2015 – Revised September 2015
26 25
RESERVED
R-0h
18 17
S
R-0h
10 9
RESERVED ADC_THMET
R-0h
2 1
PENDINGSCL
KHFSWITCHIN
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24
16
S
R-0h
8
R-0h
0
G
R-0h