Texas Instruments SimpleLink CC2620 Technical Reference Manual page 370

Interrupts and Events Registers
4.7.2.82 UDMACH21SSEL Register (Offset = 5A8h) [reset = 64h]
UDMACH21SSEL is shown in
Output Selection for DMA Channel 21 SREQ
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Field
31-7 RESERVED
6-0 EV
370
Interrupts and Events
Figure 4-91 and described in
Figure 4-91. UDMACH21SSEL Register
RESERVED
R-0h
Table 4-96. UDMACH21SSEL Register Field Descriptions
Type Reset
R 0h
R 64h
Copyright © 2015, Texas Instruments Incorporated
Table 4-96.
9
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Read only selection value
64h = Software event 0, triggered by SWEV.SWEV0
SWCU117C – February 2015 – Revised September 2015
www.ti.com
8 7 6 5 4 3 2 1
EV
R-64h
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