Texas Instruments SimpleLink CC2620 Technical Reference Manual page 442

PRCM Registers
6.2.1.10 ADCDOUBLERNANOAMPCTL Register (Offset = 24h) [reset = 0h]
ADCDOUBLERNANOAMPCTL is shown in
ADC Doubler Nanoamp Control
31 30
23 22
SPARE23
R/W-0h
15 14
7 6
RESERVED
R/W-0h
Table 6-18. ADCDOUBLERNANOAMPCTL Register Field Descriptions
Bit Field
31-25 RESERVED
24 NANOAMP_BIAS_ENABL R/W
E
23 SPARE23
22-6 RESERVED
5 ADC_SH_MODE_EN
4 ADC_SH_VBUF_EN
3-2 RESERVED
1-0 ADC_IREF_CTRL
442
Power, Reset, and Clock Management
Figure 6-16
Figure 6-16. ADCDOUBLERNANOAMPCTL Register
29 28
RESERVED
R/W-0h
21 20
13 12
RESERVED
R/W-0h
5 4
ADC_SH_MOD ADC_SH_VBU
E_EN F_EN
R/W-0h R/W-0h
Type Reset
R/W 0h
0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
and described in Table
27 26
19 18
RESERVED
R/W-0h
11 10
3 2
RESERVED
R/W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Internal. Only to be used through TI provided API.
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Internal. Only to be used through TI provided API.
Internal. Only to be used through TI provided API.
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Internal. Only to be used through TI provided API.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
6-18.
25 24
NANOAMP_BI
AS_ENABLE
R/W-0h
17 16
9 8
1 0
ADC_IREF_CTRL
R/W-0h
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