I/O Mapping And Configuration - Texas Instruments SimpleLink CC2620 Technical Reference Manual

I/O Mapping and Configuration

11.3 I/O Mapping and Configuration
The MCU IOC can map a number of peripheral modules such as GPIO, SSI (SPI), UART, I2C, and I2S to
any of the available I/Os. The peripherals AUX and JTAG are limited to specific I/O pins. Each type of
peripheral signal has a unique PORTID that can be assigned to selected I/O pins (referenced as DIOs).
lists of all the available PORTIDs.
11.3.1 Basic I/O Mapping
To map a peripheral function to DIOn, where n can range from 0 to a maximum of 31, the PORTID and
pin configuration must be set in the corresponding IOC:IOCFGn register. To select what kind of function
the pin must be routed, choose the PORTID number for the desired peripheral function and write the
PORTID number to the IOC:IOCFGn.PORTID bit field.
The function can be set by using the following driver library function:
IOCPortConfigureSet(DIOn, PORTID, PIN-CONFIG);
See Section 11.6, Unused I/O Pins to see the kind of configurations that can be set in PIN-CONFIG.
11.3.2 MAP AUXIO From the Sensor Controller to DIO Pin
There are up to 16 signals (AUXIO0 to AUXIO15) in the sensor controller domain (AUX). These signals
can be routed to specific pins given in
also be used as digital I/Os, while AUXIO8 to AUXIO15 are digital only. The signals routed from the
sensor controller domain (AUX) are configured differently than GPIO and other peripheral functions. This
section does not cover the use of all the capabilities of the sensor controller (see
Controller chapter, for more details).
In this example, AUXIO1 is mapped to DIO29 on the 7 × 7 package type and set up as a digital input. The
pin number and DIO number differs for different package types. The module must be powered, and the
clock to the specific module within the AUX domain must be enabled (AIODIO1 for AUXIO0 to AUXIO7).
1. Set the IOC:IOCFG29 PORTID bit field to 0x08 (AUX_I/O) to route AUXIO1 to DIO29.
2. The I/O signals in the AUX domain have their own open-source or open-drain configuration, which
must be set in the AUX_AIODIO:IOMODE register in the AUX domain. Set AUX_AIODIO:IOMODE.IO1
to 0x01 to enable AUXIO1 as a digital input.
3. Enable the digital input buffer for AUXIO1 by setting the IO7_0 bit field to 0x02 in the
AUX_AIODIO0:GPIODIE register.
4. The AUX latch is set to static configuration by default (values from AUXIOs are latched). Release the
latch and set in transparent mode by writing 0x01 to the AUX_WUC:AUXIOLATCH register.
11.3.2.1 Control External LNA/PA (Range Extender) With I/Os
There are four logic RF-Core internal output signals called RF Core Data Out n, where n goes from 0 to 3.
These signals can be mapped to DIOs. By default, RF Core Data Out 0 is set to go high when the LNA
must be enabled, and RF Core Data Out 1 is set high when the PA must be enabled.
describes the signals. The signals can be mapped to any DIO by setting the relevant PORTID in the
designated IOCFGn register.
Port Name
RFC_GPO0
RFC_GPO1
RFC_GPO2
RFC_GPO3
874
I/O Control
Table 11-2. AUXIO0 to AUXIO7 have analog capability, but can
Table 11-1. RF Core Data Signals for PA and LNA
PORTID
0x2F
0x30
0x31
0x32
Copyright © 2015, Texas Instruments Incorporated
Chapter
RF Core Signal
RF Core Data Out 0
RF Core Data Out 1
RF Core Data Out 2
RF Core Data Out 3 Synth calibration running
SWCU117C – February 2015 – Revised September 2015
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17, Sensor
Table 11-1
Description
LNA enable
PA enable
TX start