Texas Instruments SimpleLink CC2620 Technical Reference Manual page 178

Cortex-M3 Processor Registers
2.7.4.36 CFSR Register (Offset = D28h) [reset = 0h]
CFSR is shown in
Configurable Fault Status
This register is used to obtain information about local faults. These registers include three subsections:
The first byte is Memory Manage Fault Status Register (MMFSR). The second byte is Bus Fault Status
Register (BFSR). The higher half-word is Usage Fault Status Register (UFSR). The flags in these registers
indicate the causes of local faults. Multiple flags can be set if more than one fault occurs. These register
are read/write-clear. This means that they can be read normally, but writing a 1 to any bit clears that bit.
The CFSR is byte accessible. CFSR or its subregisters can be accessed as follows:
The following accesses are possible to the CFSR register:
- access the complete register with a word access to 0xE000ED28.
- access the MMFSR with a byte access to 0xE000ED28
- access the MMFSR and BFSR with a halfword access to 0xE000ED28
- access the BFSR with a byte access to 0xE000ED29
- access the UFSR with a halfword access to 0xE000ED2A.
31 30
23 22
RESERVED
15 14
BFARVALID RESERVED
R/W-0h
7 6
MMARVALID RESERVED
R/W-0h
Bit Field
31-26 RESERVED
25 DIVBYZERO
24 UNALIGNED
23-20 RESERVED
19 NOCP
18 INVPC
17 INVSTATE
178
Figure 2-106 and described in
Figure 2-106. CFSR Register
29 28
RESERVED
R/W-0h
21 20
R/W-0h
13 12
STKERR
R/W-0h R/W-0h
5 4
MSTKERR
R/W-0h R/W-0h
Table 2-132. CFSR Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-132.
27 26
19 18
NOCP INVPC
R/W-0h R/W-0h
11 10
UNSTKERR IMPRECISERR
R/W-0h R/W-0h
3 2
MUNSTKERR RESERVED
R/W-0h R/W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
When CCR.DIV_0_TRP (see Configuration Control Register on page
8-26) is enabled and an SDIV or UDIV instruction is used with a
divisor of 0, this fault occurs The instruction is executed and the
return PC points to it. If CCR.DIV_0_TRP is not set, then the divide
returns a quotient of 0.
When CCR.UNALIGN_TRP is enabled, and there is an attempt to
make an unaligned memory access, then this fault occurs. Unaligned
LDM/STM/LDRD/STRD instructions always fault irrespective of the
setting of CCR.UNALIGN_TRP.
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Attempt to use a coprocessor instruction. The processor does not
support coprocessor instructions.
Attempt to load EXC_RETURN into PC illegally. Invalid instruction,
invalid context, invalid value. The return PC points to the instruction
that tried to set the PC.
Indicates an attempt to execute in an invalid EPSR state (e.g. after a
BX type instruction has changed state). This includes state change
after entry to or return from exception, as well as from inter-working
instructions. Return PC points to faulting instruction, with the invalid
state.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
25 24
DIVBYZERO UNALIGNED
R/W-0h R/W-0h
17 16
INVSTATE UNDEFINSTR
R/W-0h R/W-0h
9 8
PRECISERR IBUSERR
R/W-0h R/W-0h
1 0
DACCVIOL IACCVIOL
R/W-0h R/W-0h
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