Texas Instruments SimpleLink CC2620 Technical Reference Manual page 501

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6.2.4.26 I2SCLKGR Register (Offset = 84h) [reset = 0h]
I2SCLKGR is shown in
I2S Clock Gate For Run Mode
31 30
23 22
15 14
7 6
Bit Field
31-1 RESERVED
0 CLK_EN
SWCU117C – February 2015 – Revised September 2015
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Figure 6-65 and described in
Figure 6-65. I2SCLKGR Register
29 28
RESERVED
R-0h
21 20
RESERVED
R-0h
13 12
RESERVED
R-0h
5 4
RESERVED
R-0h
Table 6-70. I2SCLKGR Register Field Descriptions
Type Reset
R 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 6-70.
27 26
19 18
11 10
3 2
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
0: Disable clock
1: Enable clock
For changes to take effect, CLKLOADCTL.LOAD needs to be written
Power, Reset, and Clock Management
PRCM Registers
25 24
17 16
9 8
1 0
CLK_EN
R/W-0h
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