Texas Instruments SimpleLink CC2620 Technical Reference Manual page 137

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Table 2-103. NVIC_ISER0 Register Field Descriptions (continued)
Bit Field
20 SETENA20
19 SETENA19
18 SETENA18
17 SETENA17
16 SETENA16
15 SETENA15
14 SETENA14
13 SETENA13
12 SETENA12
11 SETENA11
10 SETENA10
9 SETENA9
8 SETENA8
7 SETENA7
6 SETENA6
5 SETENA5
4 SETENA4
3 SETENA3
SWCU117C – February 2015 – Revised September 2015
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Type Reset Description
R/W 0h
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details).
Reading the bit returns its current enable state.
R/W 0h
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details).
Reading the bit returns its current enable state.
R/W 0h
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details).
Reading the bit returns its current enable state.
R/W 0h
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details).
Reading the bit returns its current enable state.
R/W 0h
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details).
Reading the bit returns its current enable state.
R/W 0h
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details).
Reading the bit returns its current enable state.
R/W 0h
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details).
Reading the bit returns its current enable state.
R/W 0h
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details).
Reading the bit returns its current enable state.
R/W 0h
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details).
Reading the bit returns its current enable state.
R/W 0h
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details).
Reading the bit returns its current enable state.
R/W 0h
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details).
Reading the bit returns its current enable state.
R/W 0h
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details).
Reading the bit returns its current enable state.
R/W 0h
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details).
Reading the bit returns its current enable state.
R/W 0h
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details).
Reading the bit returns its current enable state.
R/W 0h
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details).
Reading the bit returns its current enable state.
R/W 0h
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details).
Reading the bit returns its current enable state.
R/W 0h
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details).
Reading the bit returns its current enable state.
R/W 0h
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details).
Reading the bit returns its current enable state.
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Cortex-M3 Processor Registers
137