Page 1 CC13xx, CC26xx SimpleLink™ Wireless MCU Technical Reference Manual Literature Number: SWCU117C February 2015 – Revised September 2015...
Page 2: Table Of Contents
Cortex-M3 Processor Registers ..................... 2.7.1 CPU_DWT Registers ....................2.7.2 CPU_FPB Registers ....................2.7.3 CPU_ITM Registers .................... 2.7.4 CPU_SCS Registers .................... 2.7.5 CPU_TPIU Registers Contents SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 3: Table Of Contents
ICEMelter ....................Serial Wire Viewer (SWV) ......................Halt In Boot (HIB) ....................Debug and Shutdown ..............Debug Features Supported Through WUC TAP SWCU117C – February 2015 – Revised September 2015 Contents Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 4: Table Of Contents
........................Cryptography ..................10.1 AES Cryptoprocessor Overview ..................10.1.1 Functional Description ..............10.1.2 Power Management and Sleep Modes ..................10.1.3 Hardware Description Contents SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 5: Table Of Contents
1079 ....................13.3 Functional Description 1079 ..................13.3.1 GPTM Reset Conditions 1080 ....................13.3.2 Timer Modes 1080 ..................13.3.3 Wait-for-Trigger Mode 1087 SWCU117C – February 2015 – Revised September 2015 Contents Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 6: Table Of Contents
I/O Mapping 1194 ........................17.4 Modules 1195 ....................17.4.1 Sensor Controller 1195 ....................17.4.2 GPIO Control 1206 ....................17.4.3 AUX Timers 1208 Contents SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 7: Table Of Contents
Functional Description 1372 ................... 20.4.1 Bit Rate Generation 1372 ....................20.4.2 FIFO Operation 1372 ....................... 20.4.3 Interrupts 1373 ....................20.4.4 Frame Formats 1374 SWCU117C – February 2015 – Revised September 2015 Contents Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 8: Table Of Contents
1476 ......................23.3 RF Core HAL 1478 ..................... 23.3.1 Hardware Support 1478 ..................... 23.3.2 Firmware Support 1478 ..................23.3.3 Command Definitions 1491 Contents SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 9: Table Of Contents
23.7.6 Immediate Commands 1599 ......................23.8 Radio Registers 1600 ..................23.8.1 RFC_RAT Registers 1600 ..................23.8.2 RFC_DBELL Registers 1610 ..................23.8.3 RFC_PWR Registers 1626 SWCU117C – February 2015 – Revised September 2015 Contents Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 10 • Changed BATMON registers 1325 ................. • Changed register names in the UARTS chapter 1340 ......................• Changed UARTS registers 1348 Revision History SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 11 ......................• Changed Radio registers 1600 NOTE: Page numbers for previous revisions may differ from page numbers in the current version. SWCU117C – February 2015 – Revised September 2015 Revision History Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 12: Preface
SWCU117C – February 2015 – Revised September 2015 Read This First Trademarks ® SimpleLink is a trademark of Texas Instruments. ARM7, ARM CoreSight are trademarks of ARM Limited. ARM, Cortex, Thumb, AMBA, ARM PrimeCell are registered trademarks of ARM Limited. About This Document This technical reference manual provides information on how to use the CC26xx and the CC13xx SimpleLink™...
Page 13 TI's Terms of Use. TI Embedded Processors Wiki – Texas Instruments Embedded Processors Wiki TI BLE Wiki – Texas Instruments Bluetooth Smart Wiki Established to assist developers using the many Embedded Processors from TI to get started, help each other innovate, and foster the growth of general knowledge about the hardware and software surrounding these devices.
Page 14: Architectural Overview
RF nodes..........................Topic Page .................... Target Applications ......................Overview ................... Functional Overview Architectural Overview SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 15 Wireless Sensor Networks Overview Figure 1-1 shows the building blocks of the CC26xx and CC13xx devices. Figure 1-1. CC26xx and CC13xx Block Diagram SWCU117C – February 2015 – Revised September 2015 Architectural Overview Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 16: Arm Cortex-M3
[RTC]), with interrupt and 20KB of RAM with retention in all power modes positions the CC26xx and CC13xx microcontroller perfectly for battery applications. Architectural Overview SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 17: Functional Overview
Compact JTAG interface reduces the number of pins required for debugging • Ultra-low power consumption with integrated sleep modes • Up to 48-MHz operation SWCU117C – February 2015 – Revised September 2015 Architectural Overview Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 18: On-Chip Memory
(SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. Data can be transferred to and from the SRAM using the micro DMA (µDMA) controller. Architectural Overview SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 19: Radio
Features of the AES engine are as follows: • CCM, CTR, CBC-MAC, and ECB modes of operation • 118-Mbps throughput • Secure key storage memory • Low latency SWCU117C – February 2015 – Revised September 2015 Architectural Overview Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 21: System Control And Clock
The CC26xx and CC13xx devices support both asynchronous and synchronous serial communication including: • UART • • • SSI (SPI) The following subsections provide more detail on each of the communication functions. SWCU117C – February 2015 – Revised September 2015 Architectural Overview Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 22 – Supports simultaneous master and slave operation • Four I C modes: – Master transmit – Master receive – Slave transmit – Slave receive Architectural Overview SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 23 – Transmit single request asserted when there is space in the FIFO; burst request is asserted when FIFO contains four entries SWCU117C – February 2015 – Revised September 2015 Architectural Overview Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 24: Programmable I/Os
The analog comparator in this block can also be used as a higher-accuracy alternative to the ultra-low power comparator. The sensor controller takes care of baseline tracking, hysteresis, filtering, and other related functions. Architectural Overview SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 25: Random Number Generator
Four-bit IR chain for storing JTAG instructions • IEEE standard instructions: BYPASS, IDCODE, SAMPLE and PRELOAD, EXTEST and INTEST • ARM additional instructions: APACC, DPACC, and ABORT SWCU117C – February 2015 – Revised September 2015 Architectural Overview Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 26: Power Supply System
The battery voltage on the CC26xx and CC13xx device family is called VDDS (supply). This supply has the highest potential in the system and typically is the only one provided by the user. Architectural Overview SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 27 It is possible to check that the device has booted properly into external regulator mode by reading the AON_SYSCTL:PWRCTL.EXT_REG_MODE register field. SWCU117C – February 2015 – Revised September 2015 Architectural Overview Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 28: The Cortex-M3 Processor
....................Block Diagram ......................Overview ................... Programming Model ................... Cortex-M3 Core Registers ..................Instruction Set Summary ................Cortex-M3 Processor Registers The Cortex-M3 Processor SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 29 The Cortex-M3 instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers. SWCU117C – February 2015 – Revised September 2015 The Cortex-M3 Processor Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 30: Overview
To enable simple and cost-effective profiling of the system trace events, a serial wire viewer (SWV) can export a stream of software-generated messages, data trace, and profiling information through one pin. The Cortex-M3 Processor SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 31: Cortex-M3 System Component Details
Section 2.5, Coretex-M3 Core Registers. SWCU117C – February 2015 – Revised September 2015 The Cortex-M3 Processor Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 32: Exceptions And Interrupts
64-bit data transfer instructions. All instruction and data memory accesses are little endian. For more information, see the Cortex-M3/M4F Instruction Set Technical User's Manual (SPMU159). The Cortex-M3 Processor SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 33: Cortex-M3 Core Registers
PC (R15) Program status register PRIMASK FAULTMASK Exception mask registers Special registers BASEPRI CONTROL Control register Note: Banked version of SP SWCU117C – February 2015 – Revised September 2015 The Cortex-M3 Processor Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 34: Core Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA Bits Field Name Description Type Reset 31-0 DATA Register data — The Cortex-M3 Processor SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 35 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA Bits Field Name Description Type Reset 31–0 DATA Register data — SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 36 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA Bits Field Name Description Type Reset 31–0 DATA Register data — SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 37 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA Bits Field Name Description Type Reset 31–0 DATA Register data — SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 38 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA Bits Field Name Description Type Reset 31–0 DATA Register data — SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 39 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 LINK Bits Field Name Description Type Reset 31–0 LINK This field is the return address. 0xFFFF FFFF SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 40 Reads of the EPSR bits directly using the MSR instruction return 0, and the processor ignores writes to these bits. The processor ignores writes to the IPSR bits. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 41 The value of this bit is meaningful only when accessing PSR or APSR. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 42 6–0 ISRNUM IPSR ISR Number 0x00 This field contains the exception type number of the current ISR. Value Description 0x00 Thread mode SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 43 0x32-0x7F Reserved For more information, see Section 4.1.2, Exception Types. The value of this field is meaningful only when accessing PSR or IPSR. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 44 PRIMASK Priority Mask Value Description Prevents the activation of all exceptions with configurable priority No effect SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 45 Prevents the activation of all exceptions except for NMI No effect The processor clears the FAULTMASK bit on exit from any exception handler except the NMI handler. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 46 All exceptions with priority levels 5–7 are masked. All exceptions with priority levels 6 and 7 are masked. All exceptions with priority level 7 are masked. 4–0 RESERVED Reserved SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 47: Instruction Set Summary
Most instructions can use an optional condition code suffix. For more information on the instructions and operands, see the instruction descriptions in the Cortex-M3/M4F Instruction Set Technical User's Manual (SPMU159). SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 48 – LSL, LSLS Rd, Rm, <Rs|#n> Logical shift left N, Z, C LSR, LSRS Rd, Rm, <Rs|#n> Logical shift right N, Z, C SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 49 {Rd,} Rn, Op2 Subtract N, Z, C, V SUB, SUBW {Rd,} Rn, #imm12 Subtract 12-bit constant N, Z, C, V #imm Supervisor call – SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 50 Zero extend a byte – UXTH {Rd,} Rm {,ROR #n} Zero extend a halfword – – Wait for event – – Wait for interrupt – SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 51: Cortex-M3 Processor Registers
Mask 2 Section 2.7.1.16 FUNCTION2 Function 2 Section 2.7.1.17 COMP3 Comparator 3 Section 2.7.1.18 MASK3 Mask 3 Section 2.7.1.19 FUNCTION3 Function 3 Section 2.7.1.20 SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 52 Enables Interrupt overhead event. Emits an event when EXCCNT overflows (every 256 cycles of interrupt overhead). 0x0: Interrupt overhead event disabled. 0x1: Interrupt overhead event enabled. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 53 Enable CYCCNT, allowing it to increment and generate synchronization and count events. If NOCYCCNT = 1, this bit reads zero and ignore writes. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 54 (this counter will not advance in power modes where free- running clock to CPU stops). It wraps around to 0 on overflow. The debugger must initialize this to 0 when first enabling. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 55 If CTRL.CPIEVTENA is set, an event is emitted when the counter overflows. This counter initializes to 0 when it is enabled using CTRL.CPIEVTENA. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 56 An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when it is enabled using CTRL.EXCEVTENA. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 57 CPU's free-running clock. In some power modes the free-running clock to CPU is gated to minimize power consumption. This means that the sleep counter will be invalid in these power modes. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 58 An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when it is enabled using CTRL.LSUEVTENA. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 59 FOLDCNT This counts the total number folded instructions. This counter initializes to 0 when it is enabled using CTRL.FOLDEVTENA. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 60 Table 2-34. PCSR Register Field Descriptions Field Type Reset Description 31-0 EIASAMPLE Execution instruction address sample, or 0xFFFFFFFF if the core is halted. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 61 Reference value to compare against PC or the data address as given by FUNCTION0. Comparator 0 can also compare against the value of the PC Sampler Counter (CYCCNT). SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 62 So, if COMP0 is 3, this matches a word access of 0, because 3 would be within the word. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 63 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 64 PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 65 Reference value to compare against PC or the data address as given by FUNCTION1. Comparator 1 can also compare data values. So this register can contain reference values for data matching. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 66 So, if COMP1 is 3, this matches a word access of 0, because 3 would be within the word. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 67 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 68 If it is not settable then data matching is unavailable. Note 5: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 69 Table 2-41. COMP2 Register Field Descriptions Field Type Reset Description 31-0 COMP Reference value to compare against PC or the data address as given by FUNCTION2. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 70 So, if COMP2 is 3, this matches a word access of 0, because 3 would be within the word. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 71 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 72 PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 73 Table 2-44. COMP3 Register Field Descriptions Field Type Reset Description 31-0 COMP Reference value to compare against PC or the data address as given by FUNCTION3. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 74 So, if COMP3 is 3, this matches a word access of 0, because 3 would be within the word. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 75 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 76 PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 77 Comparator 3 Section 2.7.2.6 COMP4 Comparator 4 Section 2.7.2.7 COMP5 Comparator 5 Section 2.7.2.8 COMP6 Comparator 6 Section 2.7.2.9 COMP7 Comparator 7 Section 2.7.2.10 SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 78 '1'. This bit always reads 0. ENABLE Flash patch unit enable bit 0x0: Flash patch unit disabled 0x1: Flash patch unit enabled SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 79 This field always reads 3'b001. Writing to this field is ignored. 28-5 REMAP Remap base address field. RESERVED This field always reads 0. Writing to this field is ignored. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 80 Compare and remap enable comparator 0. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 0 disabled 0x1: Compare and remap for comparator 0 enabled SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 81 Compare and remap enable comparator 1. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 1 disabled 0x1: Compare and remap for comparator 1 enabled SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 82 Compare and remap enable comparator 2. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 2 disabled 0x1: Compare and remap for comparator 2 enabled SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 83 Compare and remap enable comparator 3. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 3 disabled 0x1: Compare and remap for comparator 3 enabled SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 84 Compare and remap enable comparator 4. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 4 disabled 0x1: Compare and remap for comparator 4 enabled SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 85 Compare and remap enable comparator 5. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 5 disabled 0x1: Compare and remap for comparator 5 enabled SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 86 Compare and remap enable comparator 6. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 6 disabled 0x1: Compare and remap for comparator 6 enabled SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 87 Compare and remap enable comparator 7. CTRL.ENABLE must also be set to enable comparisons. 0x0: Compare and remap for comparator 7 disabled 0x1: Compare and remap for comparator 7 enabled SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 88 Trace Enable Section 2.7.3.33 E40h Trace Privilege Section 2.7.3.34 E80h Trace Control Section 2.7.3.35 FB0h Lock Access Section 2.7.3.36 FB4h Lock Status Section 2.7.3.37 SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 89 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 90 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 91 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 92 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 93 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 94 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 95 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 96 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 97 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 98 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 99 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 100 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 101 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 102 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 103 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 104 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 105 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 106 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 107 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 108 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 109 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 110 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 111 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 112 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 113 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 114 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 115 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 116 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 117 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 118 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 119 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 120 ITM port is used concurrently by interrupts or other threads. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 121 Bit mask to enable tracing on ITM stimulus port 12. STIMENA11 Bit mask to enable tracing on ITM stimulus port 11. STIMENA10 Bit mask to enable tracing on ITM stimulus port 10. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 122 Bit mask to enable tracing on ITM stimulus port 2. STIMENA1 Bit mask to enable tracing on ITM stimulus port 1. STIMENA0 Bit mask to enable tracing on ITM stimulus port 0. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 123 Bit [3] enables stimulus ports 24, 25, ..., and 31. 0: User access allowed to stimulus ports 1: Privileged access only to stimulus ports SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 124 Enables the DWT stimulus (hardware event packet emission to the TPIU from the DWT) SYNCENA Enables synchronization packet transmission for a synchronous TPIU. CPU_DWT:CTRL.SYNCTAP must be configured for the correct synchronization speed. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 125 ITM is idle. ITMENA Enables ITM. This is the master enable, and must be set before ITM Stimulus and Trace Enable registers can be written. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 126 LOCK_ACCESS A privileged write of 0xC5ACCE55 enables more write access to Control Registers TER, TPR and TCR. An invalid write removes write access. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 127 Write access to component is blocked. All writes are ignored, reads are permitted. PRESENT Indicates that a lock mechanism exists for this component. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 128 Section 2.7.4.41 D40h ID_PFR0 Processor Feature 0 Section 2.7.4.42 D44h ID_PFR1 Processor Feature 1 Section 2.7.4.43 D48h ID_DFR0 Debug Feature 0 Section 2.7.4.44 SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 129 DCRDR Debug Core Register Data Section 2.7.4.58 DFCh DEMCR Debug Exception and Monitor Control Section 2.7.4.59 F00h STIR Software Trigger Interrupt Section 2.7.4.60 SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 130 Total number of interrupt lines in groups of 32. 0: 0...32 1: 33...64 2: 65...96 3: 97...128 4: 129...160 5: 161...192 6: 193...224 7: 225...256 SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 131 DISMCYCINT Disables interruption of multi-cycle instructions. This increases the interrupt latency of the processor becuase LDM/STM completes before interrupt stacking occurs. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 132 On reaching 0, it sets COUNTFLAG to 1 and optionally pends the SysTick handler, based on TICKINT. It then loads STRVR.RELOAD again, and begins counting. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 133 23-0 RELOAD Value to load into the SysTick Current Value Register STCVR.CURRENT when the counter reaches 0. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 134 Writing to it with any value clears the register to 0. Clearing this register also clears STCSR.COUNTFLAG. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 135 An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. The value read is valid only when core clock is at 48MHz. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 136 Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current enable state. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 137 Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current enable state. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 138 Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current enable state. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 139 Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current enable state. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 140 Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current enable state. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 141 Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current enable state. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 142 Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current enable state. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 143 Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current enable state. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 144 Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current state. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 145 Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current state. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 146 Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current state. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 147 Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current state. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 148 Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current state. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 149 Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current state. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 150 Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current state. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 151 Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current state. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 152 Reading 0 from this bit implies that interrupt line 21 is not active. Reading 1 from this bit implies that the interrupt line 21 is active (See EVENT:CPUIRQSEL21.EV for details). SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 153 Reading 0 from this bit implies that interrupt line 3 is not active. Reading 1 from this bit implies that the interrupt line 3 is active (See EVENT:CPUIRQSEL3.EV for details). SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 154 Reading 0 from this bit implies that interrupt line 0 is not active. Reading 1 from this bit implies that the interrupt line 0 is active (See EVENT:CPUIRQSEL0.EV for details). SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 155 Reading 0 from this bit implies that interrupt line 32 is not active. Reading 1 from this bit implies that the interrupt line 32 is active (See EVENT:CPUIRQSEL32.EV for details). SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 156 Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). 15-8 PRI_1 Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). PRI_0 Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 157 Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). 15-8 PRI_5 Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). PRI_4 Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 158 Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). 15-8 PRI_9 Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). PRI_8 Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 159 Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). 15-8 PRI_13 Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). PRI_12 Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 160 Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). 15-8 PRI_17 Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). PRI_16 Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 161 Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). 15-8 PRI_21 Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). PRI_20 Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 162 Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). 15-8 PRI_25 Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). PRI_24 Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 163 Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). 15-8 PRI_29 Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). PRI_28 Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 164 15-8 PRI_33 Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). PRI_32 Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 165 VARIANT Implementation defined variant number. 19-16 CONSTANT Reads as 0xF 15-4 PARTNO C23h Number of processor within family. REVISION Implementation defined revision number. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 166 17-12 VECTPENDING Pending ISR number field. This field contains the interrupt number of the highest priority pending ISR. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 167 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. VECTACTIVE Active ISR number field. Reset clears this field. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 168 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 169 1 only when the core is halted. The bit self-clears. Writing this bit to 1 while core is not halted may result in unpredictable behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 170 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 171 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 172 - LDR with PC as a destination. - BX with any register. The value written to the PC is intercepted and is referred to as the EXC_RETURN value. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 173 23-16 PRI_6 Priority of system handler 6. UsageFault 15-8 PRI_5 Priority of system handler 5: BusFault PRI_4 Priority of system handler 4: MemManage SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 174 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 175 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. PRI_12 Priority of system handler 12. Debug Monitor SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 176 0h = Exception is not active 1h = Exception is pending. USGFAULTPENDED Usage fault pending 0h = Exception is not active 1h = Exception is pending. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 177 0h = Exception is not active 1h = Exception is active MEMFAULTACT MemManage exception active 0h = Exception is not active 1h = Exception is active SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 178 Return PC points to faulting instruction, with the invalid state. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 179 XN region, even when the MPU is disabled or not present. The return PC points to the faulting instruction. MMFAR is not written. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 180 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 181 HALTED Halt request flag. The processor is halted on the next instruction. 0x0: No halt request 0x1: Halt requested by NVIC, including step SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 182 Flags CFSR.IACCVIOL, CFSR.DACCVIOL ,CFSR.MUNSTKERR and CFSR.MSTKERR in combination with CFSR.MMARVALIDindicate the cause of the fault. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 183 Flags CFSR.IBUSERR, CFSR.PRECISERR, CFSR.IMPRECISERR, CFSR.UNSTKERR and CFSR.STKERR in combination with CFSR.BFARVALID indicate the cause of the fault. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 184 Type Reset Description 31-0 IMPDEF Implementation defined. The bits map directly onto the signal assignment to the auxiliary fault inputs. Tied to 0 SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 185 32-bit basic instructions cannot.) 0x3: Thumb-2 encoding with all Thumb-2 basic instructions STATE0 State0 (T-bit == 0) 0x0: No ARM encoding 0x1: N/A SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 186 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 187 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 188 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 189 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 190 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 191 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 192 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 193 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 194 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 195 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 196 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 197 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 198 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 199 When writing to this register, 0 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 200 C_HALT Halts the core. This bit is set automatically when the core Halts. For example Breakpoint. This bit clears on core reset. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 201 C_DEBUGEN = 0. The read values for C_HALT, C_STEP and C_MASKINTS fields will be unknown to software when C_DEBUGEN = 0. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 202 0x10: XPSR/flags, execution state information, and exception number 0x11: MSP (Main SP) 0x12: PSP (Process SP) 0x14: CONTROL<<24 | FAULTMASK<<16 | BASEPRI<<8 | PRIMASK SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 203 This enables flags and bits to acknowledge state and indicate if commands have been accepted to, replied to, or accepted and replied to. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 204 It is only reset by a power-on reset. Software in the reset handler or later, or by the DAP must enable the debug monitor. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 205 VC_CORERESET Reset Vector Catch. Halt running system if Core reset occurs. Ignored when DHCSR.C_DEBUGEN is cleared. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 206 Interrupt ID field. Writing a value to this bit-field is the same as manually pending an interrupt by setting the corresponding interrupt bit in an Interrupt Set Pending Register in NVIC_ISPR0 or NVIC_ISPR1. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 207 Claim Tag Set Section 2.7.5.9 FA4h CLAIMTAG Current Claim Tag Section 2.7.5.10 FA4h CLAIMCLR Claim Tag Clear Section 2.7.5.11 FC8h DEVID Device ID Section 2.7.5.12 SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 208 0x0: Not supported 0x1: Supported 2-bit port size support 0x0: Not supported 0x1: Supported 1-bit port size support 0x0: Not supported 0x1: Supported SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 209 Writing values with more than one bit set in CSPSR, or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 210 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 12-0 PRESCALER Divisor for input trace clock is (PRESCALER + 1). SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 211 PROTOCOL Trace output protocol 0h = TracePort mode 1h = SerialWire Output (Manchester). This is the reset value. 2h = SerialWire Output (NRZ) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 212 FTNONSTOP 0: Formatter can be stopped 1: Formatter cannot be stopped RESERVED This field always reads as zero SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 213 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 214 The global synchronization trigger is generated by the Program Counter (PC) Sampler block. This means that there is no synchronization counter in the TPIU. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 215 0: This claim tag bit is not implemented 1: This claim tag bit is not implemented The behavior when writing to this register is described in CLAIMSET. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 216 0: No effect 1: Set this bit in the claim tag The behavior when reading from this location is described in CLAIMMASK. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 217 Reading CLAIMMASK determines how many bits from this register must be used. The behavior when writing to this register is described in CLAIMCLR. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 218 0: No effect 1: Clear this bit in the claim tag. The behavior when reading from this location is described in CLAIMTAG. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 219 Type Reset Description 31-0 DEVID CA0h This field returns: 0xCA1 if there is an ETM present. 0xCA0 if there is no ETM present. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 220: Cortex-M3 Peripherals Introduction
SWCU117C – February 2015 – Revised September 2015 Cortex-M3 Peripherals This chapter describes the Cortex-M3 peripherals..........................Topic Page ..............Cortex-M3 Peripherals Introduction ..................Functional Description Cortex-M3 Peripherals SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 221: Systick
This chapter provides information on the CC2650 implementation of the Cortex-M3 processor peripherals: • SysTick • NVIC • • • • • TPIU SWCU117C – February 2015 – Revised September 2015 Cortex-M3 Peripherals Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 222 The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead, providing low-latency exception handling. Cortex-M3 Peripherals SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 223 3.2.3 SCB The SCB provides system implementation information and system control, including configuration, control, and reporting of the system exceptions. SWCU117C – February 2015 – Revised September 2015 Cortex-M3 Peripherals Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 224: Tpiu
There are two configurations of the TPIU: • A configuration that supports ITM debug trace • A configuration that supports both ITM and ETM debug trace Cortex-M3 Peripherals SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 225 The DWT generates PC samples at defined intervals and interrupt event information. The DWT can also provide periodic requests for protocol synchronization to the ITM and the TPIU. SWCU117C – February 2015 – Revised September 2015 Cortex-M3 Peripherals Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 226: Cortex-M3 Memory
0x4008 4000 SRAM Low-Leakage RAM 0x2000 0000 SSI0 Synchronous Serial Interface 0 0x4000 0000 SSI1 Synchronous Serial Interface 1 0x4000 8000 226 Cortex-M3 Peripherals SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 227 UDMA0 Micro Direct Memory Access Controller 0 0x4002 0000 VIMS Versatile Instruction Memory System Control 0x4003 4000 Watchdog Timer 0x4008 0000 SWCU117C – February 2015 – Revised September 2015 Cortex-M3 Peripherals Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 228: Interrupts And Events
Fault Handling ..................... Event Fabric ..................... AON Event Fabric ..................... MCU Event Fabric ....................Memory Map ................. Interrupts and Events Registers Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 229: Exception States
Hard faults have a fixed priority of –1, meaning they have higher priority than any exception with configurable priority. SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 230: Exception Handlers
0 is the default priority for all the programmable priorities. Section 4.1.4. See CPU_SCS:SHPR 1 in Figure 2-102, SHPR1 Register (Offset = D18h) [reset = X]. 230 Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 231 AUX ADC new sample available or ADC 0x0000 00C0 DMA done, ADC underflow and overflow 0x0000 00C4 True random number generator SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 232 0x0000 0200 to 0x3FFF FE00. When configuring the CPU_SCS:VTOR register, the offset must be aligned on a 512-byte boundary. Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 233: Exception Priorities
For information about splitting the interrupt priority fields into group priority and subpriority, see Application Interrupt/Reset Control (CPU_SCS:AIRCR) in Section 2.7.4.29, AIRCR Register (Offset = D0Ch) [reset = SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 234: Exception Entry And Return
When the late-arriving exception returns from the exception handler, the normal tail-chaining rules apply. Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 235 EXC_RETURN bits 31–4 are all set. When this value is loaded into the PC, it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence. SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 236: Fault Handling
Trying to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiple instruction with ICI continuation. Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 237: Fault Escalation And Hard Faults
The processor enters a lockup state if a hard fault occurs when executing the hard fault handlers. In a CC26xx and CC13xx device, a lockup state resets the system. SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 239: Event Fabric Overview
The AON event fabric resides in the AON power domain where the wake-up controller, the debug subsystem, the AUX domain, and the real-time clock (RTC) reside. SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 240: Common Input Event List
The RTC has a programmable event, which can be configured in the RTCSEL register, and a fixed event with ID 46 (Channel 2 clear – from AUX). Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 241 GPT0A interrupt event, controlled by GPT0:TAMR.* 0x11 GPT0B GPT0B interrupt event, controlled by GPT0:TBMR.* 0x12 GPT1A GPT1A interrupt event, controlled by GPT1:TAMR.* SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 242 UART0 TX DMA burst request, controlled by UART0:DMACTL.TXDMAE UART0 TX DMA single request, controlled by 0x33 UART0_TX_DMASREQ UART0:DMACTL.TXDMAE 0x34 to 0x37 NOT_USED Always 0 242 Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 243 Events on ports configured with PORT_EVENT6 are routed here. Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. 0x5C PORT_EVENT7 Events on ports configured with PORT_EVENT7 are routed here. SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 244 0x76 AUX_DMABREQ AUX_EVCTL:DMACTL.* 0x77 AON_RTC_UPD RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 0x78 CPU_HALTED CPU halted 0x78 ALWAYS_ACTIVE Always asserted (high) Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 245: Event Subscribers
FRZSEL0 register. Table 4-7. Freeze Subscriber Event Selection Event Number Event Enumeration NONE 0x78 CPU_HALTED 0x79 ALWAYS_ACTIVE SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 246: Memory Map
BATMON_VOLT BATMON voltage update event 0x37 AUX_COMPB_ASYNC Comparator B triggered 0x38 AUX_COMPB_ASYNC_N Comparator B not triggered 0x3F NONE No event Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 247: Interrupts And Events Registers
Section 4.7.1.2 EVTOMCUSEL Event Selector For MCU Event Fabric Section 4.7.1.3 RTCSEL RTC Capture Event Selector For AON_RTC Section 4.7.1.4 SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 248 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 249 2Fh = Comparator A triggered 30h = Comparator B triggered 31h = ADC conversion completed 32h = TDC completed or timed out SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 250 27h = RTC channel 1 - delayed event 28h = RTC channel 2 - delayed event 29h = RTC combined delayed event Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 251 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 252 2Fh = Comparator A triggered 30h = Comparator B triggered 31h = ADC conversion completed 32h = TDC completed or timed out Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 253 27h = RTC channel 1 - delayed event 28h = RTC channel 2 - delayed event 29h = RTC combined delayed event SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 254 38h = Comparator B not triggered. Asynchronous signal directly from AUX Comparator B (inverted) as opposed to AUX_COMPB, which is synchronized in AUX 3Fh = No event, always low Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 255 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 256 2Fh = Comparator A triggered 30h = Comparator B triggered 31h = ADC conversion completed 32h = TDC completed or timed out Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 257 27h = RTC channel 1 - delayed event 28h = RTC channel 2 - delayed event 29h = RTC combined delayed event SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 258 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 259 2Fh = Comparator A triggered 30h = Comparator B triggered 31h = ADC conversion completed 32h = TDC completed or timed out SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 260 38h = Comparator B not triggered. Asynchronous signal directly from AUX Comparator B (inverted) as opposed to AUX_COMPB, which is synchronized in AUX 3Fh = No event, always low Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 261 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 262 30h = Comparator B triggered 31h = ADC conversion completed 32h = TDC completed or timed out 33h = AUX Timer 0 Event Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 263 29h = RTC combined delayed event 2Ah = RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 264 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 265 30h = Comparator B triggered 31h = ADC conversion completed 32h = TDC completed or timed out 33h = AUX Timer 0 Event SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 266 38h = Comparator B not triggered. Asynchronous signal directly from AUX Comparator B (inverted) as opposed to AUX_COMPB, which is synchronized in AUX 3Fh = No event, always low Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 267 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 268 31h = ADC conversion completed 32h = TDC completed or timed out 33h = AUX Timer 0 Event 34h = AUX Timer 1 Event Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 269 38h = Comparator B not triggered. Asynchronous signal directly from AUX Comparator B (inverted) as opposed to AUX_COMPB, which is synchronized in AUX 3Fh = No event, always low SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 270: Event Registers
120h RFCSEL8 Output Selection for RFC Event 8 Section 4.7.2.43 124h RFCSEL9 Output Selection for RFC Event 9 Section 4.7.2.44 Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 271 Section 4.7.2.89 600h GPT3ACAPTSEL Output Selection for GPT3 0 Section 4.7.2.90 604h GPT3BCAPTSEL Output Selection for GPT3 1 Section 4.7.2.91 SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 272 Section 4.7.2.94 A00h FRZSEL0 Output Selection for FRZ Subscriber 0 Section 4.7.2.95 F00h SWEV Set or Clear Software Events Section 4.7.2.96 Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 273 Read only selection value 4h = Edge detect event from IOC. Configured by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 274 Read only selection value 9h = Interrupt event from I2C Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 275 1Eh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event. SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 276 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 277 Read only selection value 7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 278 Read only selection value 24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 279 1Ch = AUX software event 0, triggered by AUX_EVCTL:SWEVSET.SWEV0, also available as AUX_EVENT0 AON wake-up event. MCU domain wake-up control AON_EVENT:MCUWUSEL AUX domain wake-up control AON_EVENT:AUXWUSEL SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 280 Read only selection value 22h = SSI0 combined interrupt, interrupt flags are found here SSI0:MIS Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 281 Read only selection value 23h = SSI0 combined interrupt, interrupt flags are found here SSI1:MIS SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 282 1Bh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event. Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 283 Read only selection value 1Ah = Combined RCF hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 284 Read only selection value 19h = RFC Doorbell Command Acknowledgment Interrupt, equivalent to RFC_DBELL:RFACKIFG.ACKFLAG Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 285 Read only selection value 8h = Interrupt event from I2S SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 286 1Dh = AUX software event 1, triggered by AUX_EVCTL:SWEVSET.SWEV1, also available as AUX_EVENT2 AON wake up event. MCU domain wake-up control AON_EVENT:MCUWUSEL AUX domain wake-up control AON_EVENT:AUXWUSEL Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 287 Read only selection value 18h = Watchdog interrupt event, controlled by WDT:CTL.INTEN SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 288 Read only selection value 10h = GPT0A interrupt event, controlled by GPT0:TAMR Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 289 Read only selection value 11h = GPT0B interrupt event, controlled by GPT0:TBMR SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 290 Read only selection value 12h = GPT1A interrupt event, controlled by GPT1:TAMR Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 291 Read only selection value 13h = GPT1B interrupt event, controlled by GPT1:TBMR SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 292 Read only selection value Ch = GPT2A interrupt event, controlled by GPT2:TAMR Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 293 Read only selection value Dh = GPT2B interrupt event, controlled by GPT2:TBMR SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 294 Read only selection value Eh = GPT3A interrupt event, controlled by GPT3:TAMR Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 295 Read only selection value Fh = GPT3B interrupt event, controlled by GPT3:TBMR SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 296 Read only selection value 5Dh = CRYPTO result available interrupt event, the corresponding flag is found here CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by CRYPTO:IRQSTAT.RESULT_AVAIL Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 297 Read only selection value 27h = Combined DMA done, corresponding flags are here UDMA0:REQDONE SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 298 Read only selection value 26h = DMA bus error, corresponds to UDMA0:ERROR.STATUS Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 299 Read only selection value 15h = FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 300 Read only selection value 64h = Software event 0, triggered by SWEV.SWEV0 Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 301 Read only selection value Bh = AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 302 Read only selection value 1h = AON programmable event 0. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG0_EV Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 303 72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 304 Read only selection value 6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 305 Read only selection value 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 306 Read only selection value 68h = TRNG Interrupt event, controlled by TRNG:IRQEN.EN Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 307 Read only selection value 3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 308 Read only selection value 3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 309 Read only selection value 3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 310 Read only selection value 40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 311 Read only selection value 41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 312 Read only selection value 42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 313 Read only selection value 43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 314 Read only selection value 44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 315 Read only selection value 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 316 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 317 AUX_EVCTL:EVTOMCUFLAGS.OBSMUX0 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS 79h = Always asserted SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 318 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 319 AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 6Fh = Auto-take event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 320 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 321 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 322 AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 6Fh = Auto-take event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 323 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 324 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 325 AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 6Fh = Auto-take event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 326 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 327 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 328 AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 6Fh = Auto-take event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 329 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 330 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 331 AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 6Fh = Auto-take event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 332 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 333 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 334 AUX_EVCTL:EVTOMCUFLAGS.TIMER0_EV 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 6Fh = Auto-take event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 335 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 336 Read only selection value 31h = UART0 RX DMA single request, controlled by UART0:DMACTL.RXDMAE Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 337 Read only selection value 30h = UART0 RX DMA burst request, controlled by UART0:DMACTL.RXDMAE SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 338 Read only selection value 33h = UART0 TX DMA single request, controlled by UART0:DMACTL.TXDMAE Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 339 Read only selection value 32h = UART0 TX DMA burst request, controlled by UART0:DMACTL.TXDMAE SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 340 Read only selection value 29h = SSI0 RX DMA single request, controlled by SSI0:DMACR.RXDMAE Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 341 Read only selection value 28h = SSI0 RX DMA burst request , controlled by SSI0:DMACR.RXDMAE SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 342 Read only selection value 2Bh = SSI0 TX DMA single request, controlled by SSI0:DMACR.TXDMAE Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 343 Read only selection value 2Ah = SSI0 TX DMA burst request , controlled by SSI0:DMACR.TXDMAE SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 344 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 345 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 346 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 347 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 348 Read only selection value 75h = DMA single request event from AUX, configured by AUX_EVCTL:DMACTL Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 349 Read only selection value 76h = DMA burst request event from AUX, configured by AUX_EVCTL:DMACTL SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 350 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Read only selection value 74h = AUX observation loopback Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 351 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Read only selection value 74h = AUX observation loopback SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 352 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 79h = Always asserted Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 353 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 79h = Always asserted SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 354 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 79h = Always asserted Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 355 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 79h = Always asserted SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 356 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 79h = Always asserted Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 357 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 79h = Always asserted SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 358 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 79h = Always asserted Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 359 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 79h = Always asserted SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 360 Read only selection value 3h = AON programmable event 2. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG2_EV Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 361 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 362 24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS 26h = DMA bus error, corresponds to UDMA0:ERROR.STATUS 27h = Combined DMA done, corresponding flags are here Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 363 PORT_EVENT4 will be routed here. 5Bh = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 364 76h = DMA burst request event from AUX, configured by AUX_EVCTL:DMACTL 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 78h = CPU halted 79h = Always asserted Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 365 Read only selection value 7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 366 Read only selection value 2Dh = SSI1 RX DMA single request, controlled by SSI0:DMACR.RXDMAE Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 367 Read only selection value 2Ch = SSI1 RX DMA burst request , controlled by SSI0:DMACR.RXDMAE SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 368 Read only selection value 2Fh = SSI1 TX DMA single request, controlled by SSI0:DMACR.TXDMAE Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 369 Read only selection value 2Eh = SSI1 TX DMA burst request , controlled by SSI0:DMACR.TXDMAE SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 370 Read only selection value 64h = Software event 0, triggered by SWEV.SWEV0 Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 371 Read only selection value 64h = Software event 0, triggered by SWEV.SWEV0 SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 372 Read only selection value 65h = Software event 1, triggered by SWEV.SWEV1 Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 373 Read only selection value 65h = Software event 1, triggered by SWEV.SWEV1 SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 374 Read only selection value 66h = Software event 2, triggered by SWEV.SWEV2 Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 375 Read only selection value 66h = Software event 2, triggered by SWEV.SWEV2 SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 376 Read only selection value 67h = Software event 3, triggered by SWEV.SWEV3 Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 377 Read only selection value 67h = Software event 3, triggered by SWEV.SWEV3 SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 378 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 379 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 6Fh = Auto-take event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE 70h = AUX ADC done, corresponds to SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 380 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 381 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 382 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.TIMER1_EV 6Fh = Auto-take event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE 70h = AUX ADC done, corresponds to Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 383 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 384 12h = GPT1A interrupt event, controlled by GPT1:TAMR 13h = GPT1B interrupt event, controlled by GPT1:TBMR 79h = Always asserted Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 385 Read only selection value 63h = Watchdog non maskable interrupt event, controlled by WDT:CTL.INTTYPE SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 386 61h = RFC RAT event 6, configured by RFC_RAT:RATEV.OEVT6 62h = RFC RAT event 7, configured by RFC_RAT:RATEV.OEVT7 79h = Always asserted Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 387 Read/write selection value 0h = Always inactive 78h = CPU halted 79h = Always asserted SWCU117C – February 2015 – Revised September 2015 Interrupts and Events Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 388 SWEV0 Writing "1" to this bit when the value is "0" triggers the Software 0 event. Interrupts and Events SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 389: Jtag Interface
Serial Wire Viewer (SWV) ....................Halt In Boot (HIB) ..................Debug and Shutdown ............ Debug Features Supported Through WUC TAP ....................Profiler Register SWCU117C – February 2015 – Revised September 2015 JTAG Interface Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 390: Top Level Debug System
The debug subsystem also implements a firewall for unauthorized access to debug/test ports. Figure 5-1 shows a block diagram of debug subsystem. JTAG Interface SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 391 MCU voltage domain 1149.1 eFuse TAP PRCM PBIST1.0 TAP PBIST2.0 TAP JTAG power domain Test TAP 1149.1 ICEPick cJTAG 2/4pin ICEMelter I/O MUX SWCU117C – February 2015 – Revised September 2015 JTAG Interface Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 392 The two main paths allow for setting or retrieving information from either a data register (DR) or the instruction register (IR) of the device. The data register depends on the value loaded into the instruction register. JTAG Interface SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 393: Cjtag
Reuse of TDI and TDO pins TCKWID Programmable TCK width Power down logic capability for Power control Power down logic cJTAG module SWCU117C – February 2015 – Revised September 2015 JTAG Interface Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 394 OScan4 nTDI nTDI OScan5 nTDI nTDI OScan6 nTDI OScan7 nTDI TMS is present for the first packet of the shift. JTAG Interface SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 395: Jtag Commands
No DTS delay is added Add one TCKC signal period Add two TCKC signal periods Add a variable number of TCKC signal periods Reserved SWCU117C – February 2015 – Revised September 2015 JTAG Interface Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 396 SGC bit of a nontargeted controller is cleared SGC bit of the targeted controller is set SGC bit of a nontargeted controller is not affected 00101–00110 Reserved 396 JTAG Interface SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 397: Programming Sequences
3. Scan DR (9 bits of 1, end in Pause DR): Load CP1 with 9. 4. Goto Scan (Through Update DR to Pause DR): Complete CP1 by going through update. SWCU117C – February 2015 – Revised September 2015 JTAG Interface Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 398: Icepick
TAPs for end user. The open TAPs can be locked by writing to the corresponding field in the customer configuration area. 398 JTAG Interface SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 399 TAP is connected closest to the device TDO. • Any selected TAPs within the test bank are linked before any TAPs within the debug bank (for example, DAP). SWCU117C – February 2015 – Revised September 2015 JTAG Interface Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 400: Icepick Registers
000000, 111111 BYPASS Always-open ROUTER Connected IDCODE Always-open ICEPICKCODE Always-open CONNECT Always-open 1000 USERCODE Always-open 000001, 000011, 000110, Reserved Reserved 001001–111110 JTAG Interface SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 401 The contents of this register are replicated to a device configuration area which is memory mapped. Refer to FCFG1:ICEPICK_DEVICE_ID in Section 9.2.1.50 for details of this register. SWCU117C – February 2015 – Revised September 2015 JTAG Interface Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 402 An identifier of the ICEpick Type ICEpick Type This field is set to 0x1CC, which corresponds to Type C. Capabilities Reserved JTAG Interface SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 403: Router Scan Chain
Block Select 001: Test TAP Linking Control Block (see Section 5.3.4.2) 010: Debug TAP Linking Control Block (see Section 5.3.4.3) 011–111: Reserved SWCU117C – February 2015 – Revised September 2015 JTAG Interface Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 404: Tap Routing Registers
This register is a dummy register that returns 0 when read. Writes are ignored. There are not any side effects to writing or reading this register. JTAG Interface SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 405 When activated, the ICEPick TAP is no longer visible between the device Disappear-forever TDI and TDO. Only a power-on reset makes the TAP visible again. 001–010, 100–111 Reserved Reserved SWCU117C – February 2015 – Revised September 2015 JTAG Interface Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 406 Table 5-20 for more details. Table 5-20. Debug TAP Linking Registers Register Register Name Secondary Debug TAP 0 Register 0x1–0xF Reserved JTAG Interface SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 407 The value read does not reflect the value written until the – power and clock controller has acted upon a change in the written value. Reserved – Reserved SWCU117C – February 2015 – Revised September 2015 JTAG Interface Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 408: Icemelter
Writes to the CPU_ITM:STIMn registers (assuming that they are enabled) trigger a transmit on SWV output if the FIFO is not full. JTAG Interface SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 409: Halt In Boot (Hib)
NOTE: If either of these considerations occur, the boot code (before handing control to the application code) waits in a loop until an I/O wake-up event occurs. SWCU117C – February 2015 – Revised September 2015 JTAG Interface Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 410: Debug Features Supported Through Wuc Tap
1: Do not reset WUC tap when the JTAG power domain is powered IR 0x04 JTAG_DO_NOT_RESET down. Bit 4 in DR[6:0] 0: WUC is reset when the JTAG power domain is powered down. JTAG Interface SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 411: Profiler Register
0x6 The RF synthesizer is active 0xE The RF core is receiving a packet 0xA The RF core is transmitting a packet Others: Reserved 11–0 Reserved SWCU117C – February 2015 – Revised September 2015 JTAG Interface Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 412: Power, Reset, And Clock Management
This chapter details the flexible power management and clock control (PRCM) of the CC26xx and CC13xx devices..........................Topic Page ..................... Introduction ....................PRCM Registers Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 413: Introduction
Power cycling down and up takes a longer time than VD power off. Chip loses all configurations and Voltage regulator off boots at wakeup. Gives the least possible current consumption. SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 414: System Cpu Mode
WFI or WFE active and CPU_SCS:SCR.SLEEPDEEP = 0 Deepsleep mode WFI or WFE active and CPU_SCS:SCR.SLEEPDEEP = 1 Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 415: Supply System
Both of these bits must be cleared to power down RFCORE_PD. SERIAL_PD is SW-controlled by PRCM:PDCTL0.SERIAL_ON. SERIAL_PD PERIPH_PD is SW-controlled by PRCM:PDCTL0.PERIPH_ON. PERIPH_PD SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 416 Global LDO and the internal DC-DC regulator. Refer to the reference design for a detailed description of connections and decoupling in the external regulator mode. Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 417: Digital Power Partitioning
I/O state holder AUX Wakeup Analog interface Timers Event Peripherals SC SRAM Event fabric JTAG_PD ICEPick JTAG router IEEE1149.7 (cJTAG) SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 418: Clock Management
24 MHz ACLK_ADC oscillator 32 kHz LF RC ACLK_REF oscillator 32 kHz External ACLK_TDC I/O controller 32 kHz Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 419 24 MHz from RC oscillator ACLK_TDC Used as clock for TDC 24 MHz from XTAL oscillator Selectable in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 420 DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL RCOSC 48 MHz / 1536 XTAL 48 MHz / 768 ACLK_REF RCOSC 32 kHz XTAL 32.768 kHz Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 421 SCLK_HF, regardless of the settings in PRCM:INFCLKDIVR/S/DS. SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 422 2 if PRCM:INFCLKDIVR/S/ DS = 1 I/O controller INFRASTRUCTURE clock Wakeup interrupt controller Watchdog timer Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 423 Clocks in AON_VD All modules in AON_VD run on SCLK_LF except AUX_PD. Clocks to AUX_PD are user configurable. SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 424: Power Modes
When an emulator/debugger is attached to the device, the wake up time is approximately 200 µs shorter as the system does not enter true standby. Brown Out Detector is disabled between recharge periods in Standby. Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 426 The SCLK_LF clock is derived from one of the following clock sources: – 32-kHz RC oscillator – 32.768-kHz crystal oscillator 426 Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 427 Set the system CPU SLEEPDEEP bit CPU_SCS:SCR.SLEEPDEEP Stop the system CPU to start the WFI or WFE power-down sequence SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 428: Reset
The following resets cannot be disabled and, when triggered, always result in a system reset: • Power-on reset • Pin reset • VDDS failure • VDDR failure • VDD failure Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 429 6.1.6.5 Reset of AON_VD AON_VD is reset by a system reset. See Section 6.1.6.1, System Resets, for details. SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 430 Introduction www.ti.com 6.1.6.6 Reset of AUX_PD Reset of AUX_PD can be done by writing to the AON_WUC:AUXCTL.RESET_REQ register. Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 431: Prcm Registers
RCOSCHF Control Section 6.2.1.13 STAT0 Status 0 Section 6.2.1.14 STAT1 Status 1 Section 6.2.1.15 STAT2 Status 2 Section 6.2.1.16 SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 432 STAT0.PENDINGSCLKHFSWITCHING) sclk_hf switching must be disabled to prevent flash corruption. Switching must not be enabled when running from flash. Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 433 Internal. Only to be used through TI provided API. SCLK_HF_SRC_SEL Source select for sclk_hf 0h = High frequency RCOSC clk 1h = High frequency XOSC clk SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 434 XOSC_HF_FAST_START R/W Internal. Only to be used through TI provided API. Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 435 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 436 Internal. Only to be used through TI provided API. IBIASCAP_HPTOLP_OL_ R/W Internal. Only to be used through TI provided API. Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 437 Internal. Only to be used through TI provided API. HPMRAMP1_TH Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 438 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 439 Internal. Only to be used through TI provided API. 15-0 XOSC_HF_COLUMN_Q1 Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 440 13-0 XOSC_HF_IBIASTHERM Internal. Only to be used through TI provided API. Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 441 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 442 ADC_IREF_CTRL Internal. Only to be used through TI provided API. Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 443 Internal. Only to be used through TI provided API. LP_BUF_ITRIM Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 444 Internal. Only to be used through TI provided API. RCOSCLF_CTUNE_TRIM R/W Internal. Only to be used through TI provided API. Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 445 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 446 It will be enabled if 24 or 48 MHz chrystal is used (enabled in doulbler bypass for the 48MHz chrystal). Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 447 ADC_DATA adc_data PENDINGSCLKHFSWITC R Indicates when sclk_hf is ready to be swtiched HING SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 448 The vaue is an unsigned interger. It is used for debug only. FORCE_RCOSC_HF force_rcosc_hf SCLK_HF_EN SCLK_HF_EN SCLK_MF_EN SCLK_MF_EN ACLK_ADC_EN ACLK_ADC_EN ACLK_TDC_EN ACLK_TDC_EN ACLK_REF_EN ACLK_REF_EN CLK_CHP_EN CLK_CHP_EN CLK_DCDC_EN CLK_DCDC_EN Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 449 Reset Description SCLK_HF_GOOD SCLK_HF_GOOD SCLK_MF_GOOD SCLK_MF_GOOD SCLK_LF_GOOD SCLK_LF_GOOD ACLK_ADC_GOOD ACLK_ADC_GOOD ACLK_TDC_GOOD ACLK_TDC_GOOD ACLK_REF_GOOD ACLK_REF_GOOD CLK_CHP_GOOD CLK_CHP_GOOD CLK_DCDC_GOOD CLK_DCDC_GOOD SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 450 +/- 20 ppm and xosc_hf is good for radio operations. Used for SW to start synthesizer. Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 451: Aon_Sysctl Registers
Register Name Section PWRCTL Power Management Section 6.2.2.1 RESETCTL Reset Management Section 6.2.2.2 SLEEPCTL Sleep Mode Section 6.2.2.3 SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 452 1: Use DCDC for recharge of VDDR Note: This bitfield must be set to the same as DCDC_ACTIVE Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 453 1: A wakeup has occurred from SHUTDOWN Note: This flag can not be cleared and will therefor remain valid untill poweroff/reset SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 454 DDI_0_OSC:CTL0.CLK_LOSS_EN 0: Clock loss is ignored 1: Clock loss generates system reset Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 455 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 456 Application software may want to reconfigure the state for all IO's before setting this bitfield upon waking up from a SHUTDOWN. Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 457: Aon_Wuc Registers
Recharge Controller Status Section 6.2.3.11 OSCCFG Oscillator Configuration Section 6.2.3.12 JTAGCFG JTAG Configuration Section 6.2.3.13 JTAGUSERCODE JTAG USERCODE Section 6.2.3.14 SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 458 0h = No clock in Powerdown 1h = Use SCLK_LF in Powerdown Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 459 NB: Switching the clock source is guaranteed to be glitchless 1h = HF Clock (SCLK_HF) 4h = LF Clock (SCLK_LF) SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 460 7h = Retention on for SRAM:BANK0, SRAM:BANK1 and SRAM:BANK2 Fh = Retention on for all banks (SRAM:BANK0, SRAM:BANK1 ,SRAM:BANK2 and SRAM:BANK3) Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 461 NB: If retention is disabled, the AUX_RAM will be powered off when it would otherwise be put in retention mode SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 462 0: AUX is allowed to Power Off, Power Down or Disconnect. 1: AUX Power OFF, Power Down or Disconnect requests will be overruled Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 463 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 464 At this time, the will not enter Powerdown mode, but instead it will turn off all internal powersupplies, effectively putting the device into Shutdown mode. Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 465 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 466 1: Last MCU reset was a warm reset (requested from MCU or JTAG as indicated in MCU_RESET_SRC) This bit can only be cleared by writing a 1 to it Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 467 PERIOD will effectively be a 16 bit value coded in a 5 bit mantissa and 3 bit exponent: This field sets the Mantissa of the Period. PER_E PERIOD=(PER_M*16+15)*2 SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 468 PERIOD will effectively be a 16 bit value coded in a 5 bit mantissa and 3 bit exponent: This field sets the Exponent of the Period. PER_E PERIOD=(PER_M*16+15)*2 Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 469 We can therefore use the value as an indication of the leakage current during recharge. This bitfield is cleared to 0 when writing this register. SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 470 This field sets the exponent Note: Oscillator amplitude calibration is turned of when both PER_M and this bitfield are set to 0 Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 471 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 472 Description 31-0 USER_CODE B99A02Fh 32-bit JTAG USERCODE register feeding main JTAG TAP NB: This field can be locked Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 473 SERIAL Power Domain Control Section 6.2.4.40 138h PDCTL0PERIPH PERIPH Power Domain Control Section 6.2.4.41 140h PDSTAT0 Power Domain Status Section 6.2.4.42 SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 474 VIMS Power Domain Status Section 6.2.4.54 1D0h RFCMODESEL Selected RFC Mode Section 6.2.4.55 224h RAMRETEN Memory Retention Control Section 6.2.4.56 Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 475 0h = Divide by 1 1h = Divide by 2 2h = Divide by 8 3h = Divide by 32 SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 476 0h = Divide by 1 1h = Divide by 2 2h = Divide by 8 3h = Divide by 32 Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 477 0h = Divide by 1 1h = Divide by 2 2h = Divide by 8 3h = Divide by 32 SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 478 4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 (Note: Setting must be loaded with CLKLOADCTL.LOAD) 5. RFC do no request access to BUS 6. System CPU in deepsleep Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 479 0 : One or more registers have been write accessed after last LOAD 1 : No registers are write accessed after last LOAD SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 480 - UARTCLKGDS - I2SCLKGR - I2SCLKGS - I2SCLKGDS - I2SBCLKSEL - I2SCLKCTL - I2SMCLKDIV - I2SBCLKDIV - I2SWCLKDIV Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 481 1: Enable clock if RFC power domain is on For changes to take effect, CLKLOADCTL.LOAD needs to be written SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 482 01: Disable clock when SYSBUS clock is disabled 11: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 483 For changes to take effect, CLKLOADCTL.LOAD needs to be written CRYPTO_CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 484 For changes to take effect, CLKLOADCTL.LOAD needs to be written CRYPTO_CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 485 For changes to take effect, CLKLOADCTL.LOAD needs to be written CRYPTO_CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 486 CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 487 CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 488 CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 489 2h = Enable clock for GPT1 4h = Enable clock for GPT2 8h = Enable clock for GPT3 SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 490 2h = Enable clock for GPT1 4h = Enable clock for GPT2 8h = Enable clock for GPT3 Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 491 2h = Enable clock for GPT1 4h = Enable clock for GPT2 8h = Enable clock for GPT3 SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 492 CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 493 CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 494 CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 495 CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 496 CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 497 CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 498 For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for SSI0 2h = Enable clock for SSI1 Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 499 For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for SSI0 2h = Enable clock for SSI1 SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 500 For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for SSI0 2h = Enable clock for SSI1 Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 501 CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 502 CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 503 CLK_EN 0: Disable clock 1: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 504 Internal. Only to be used through TI provided API. RATIO Internal. Only to be used through TI provided API. Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 505 0: Use external BCLK 1: Use internally generated clock For changes to take effect, CLKLOADCTL.LOAD needs to be written SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 506 5h = Divide by 32 6h = Divide by 64 7h = Divide by 128 8h = Divide by 256 Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 507 1: Enables the generation of MCLK, BCLK and WCLK For changes to take effect, CLKLOADCTL.LOAD needs to be written SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 508 If MDIV is odd the low phase of the clock is one MCUCLK period longer than the high phase. For changes to take effect, CLKLOADCTL.LOAD needs to be written Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 509 MCUCLK period longer than the low phase. For changes to take effect, CLKLOADCTL.LOAD needs to be written SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 510 WCLK = MCUCLK / (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz] For changes to take effect, CLKLOADCTL.LOAD needs to be written Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 511 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 512 1: A WDT event has occured since last SW clear of the register. A read of this register clears both WDT_STAT and LOCKUP_STAT. Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 513 RFC_ON 0: RFC power domain powered off if also PDCTL1.RFC_ON = 0 1: RFC power domain powered on SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 514 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Alias for PDCTL0.RFC_ON Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 515 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Alias for PDCTL0.SERIAL_ON SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 516 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Alias for PDCTL0.PERIPH_ON Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 517 1: Domain powered up (guaranteed) RFC_ON RFC Power domain 0: Domain may be powered down 1: Domain powered up (guaranteed) SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 518 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Alias for PDSTAT0.RFC_ON Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 519 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Alias for PDSTAT0.SERIAL_ON SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 520 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Alias for PDSTAT0.PERIPH_ON Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 521 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 522 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. This is an alias for PDCTL1.CPU_ON Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 523 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. This is an alias for PDCTL1.RFC_ON SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 524 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. This is an alias for PDCTL1.VIMS_MODE Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 525 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 526 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. This is an alias for PDSTAT1.BUS_ON Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 527 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. This is an alias for PDSTAT1.RFC_ON SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 528 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. This is an alias for PDSTAT1.CPU_ON Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 529 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. This is an alias for PDSTAT1.VIMS_MODE SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 530 4h = Select Mode 4 5h = Select Mode 5 6h = Select Mode 6 7h = Select Mode 7 Power, Reset, and Clock Management SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 531 Must remain in GPRAM mode after wake up, alternatively select OFF mode first and then CACHE or SPILT mode. 10: Illegal mode 11: No restrictions SWCU117C – February 2015 – Revised September 2015 Power, Reset, and Clock Management Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 532: Versatile Instruction Memory System (Vims)
The RAM block can be used as a cache for the Flash block or as general purpose RAM. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 533 VIMS Software Remarks ............................................. FLASH ..............Power Management Requirements ....................ROM Functions ......................SRAM ....................VIMS Registers SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 534: Vims Configurations
The VIMS:CTL.MODE register is blocked for updates during a mode change. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 535 Figure 7-4. VIMS Module in Off Mode icode/dcode GPRAM SYSCODE and USERCODE address space icode/dcode FLASH sysbus sysbus BROM address space SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 536 The line buffer prevents both TAG and CACHE lookup if the data is already in the line buffer. The cache line buffer is cleared as a part of the invalidation scheme. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 537: Vims Flash Line Buffering
CPU is not running at full speed, there is no performance optimization; therefore the TAG prefetch system must be disabled. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 538: Vims Software Remarks
Mode 1 can also be used when the system is in GPRAM mode, but software must take into account that the data in the GPRAM is lost when the system is set in retention. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 539: Flash
7.4.1 FLASH Memory Protection The FLASH memory can be read/write protected in 4-KB sectors by configuring the CCFG. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 540: Memory Programming
In this mode, switching to Active Read is done without any reduced read latency. • Reading: Flash is actively reading without any power reduction. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 541 Voltage off by PRCM Voltage Off, reset asserted Oscillator Requirements None/uncalibrated Holes allowed Calibrated 48 MHz Figure 7-9. Flash Power States SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 542: Rom Functions
GPIO backdoor. The bootloader may not be called from application code. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 543: Sram
Data can also be transferred to and from the SRAM using the micro direct memory access controller (μDMA). The Cortex M0 in the RF Core also has access to the system RAM. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 544: Vims Registers
FMC Module Status Section 7.8.1.40 2064h FLOCK FMC Flash Lock Section 7.8.1.41 2080h FVREADCT FMC VREADCT Trim Section 7.8.1.42 Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 545 Section 7.8.1.87 2260h FSM_PGM FMC FSM Program Bits Section 7.8.1.88 2264h FSM_ERA FMC FSM Erase Bits Section 7.8.1.89 SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 546 FMC Flash Bank 7 Starting Address Section 7.8.1.122 2430h FCFG_B0_SSIZE0 FMC Flash Bank 0 Sector Size 0 Section 7.8.1.123 Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 547 0 : Not busy 1 : Busy POWER_MODE Power state of the flash sub-system. 0 : Active 1 : Low power SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 548 Internal. Only to be used through TI provided API. DIS_IDLE Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 549 Internal. Only to be used through TI provided API. SYSCODE_START Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 550 Internal. Only to be used through TI provided API. SECTORS Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 551 Internal. Only to be used through TI provided API. FWLOCK Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 552 Internal. Only to be used through TI provided API. FWFLAG Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 553 Internal. Only to be used through TI provided API. 15-0 DUMPWORD Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 554 Internal. Only to be used through TI provided API. 10-0 Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 555 Internal. Only to be used through TI provided API. Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 556 Table 7-13. DATALOWER Register Field Descriptions Field Type Reset Description 31-0 DATA Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 557 Internal. Only to be used through TI provided API. GATING Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 558 Internal. Only to be used through TI provided API. RESETDONE Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 559 Internal. Only to be used through TI provided API. 23-0 ACCUMULATOR Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 560 Internal. Only to be used through TI provided API. INPUTENABLE Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 561 Internal. Only to be used through TI provided API. Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 562 Table 7-19. EFUSEKEY Register Field Descriptions Field Type Reset Description 31-0 CODE Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 563 Internal. Only to be used through TI provided API. EFUSEDAY Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 564 Internal. Only to be used through TI provided API. SYS_WS_READ_STATE Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 565 Internal. Only to be used through TI provided API. DATA Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 566 Internal. Only to be used through TI provided API. MARGIN Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 567 Internal. Only to be used through TI provided API. WRITECLOCK Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 568 Internal. Only to be used through TI provided API. CODE Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 569 Internal. Only to be used through TI provided API. FROM0 Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 570 Internal. Only to be used through TI provided API. FROM0 Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 571 Table 7-28. SELFTESTCYC Register Field Descriptions Field Type Reset Description 31-0 CYCLES Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 572 Table 7-29. SELFTESTSIGN Register Field Descriptions Field Type Reset Description 31-0 SIGNATURE Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 573 Internal. Only to be used through TI provided API. Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 574 Internal. Only to be used through TI provided API. Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 575 Internal. Only to be used through TI provided API. 23-0 EDACEN Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 576 Internal. Only to be used through TI provided API. 23-0 ERR_PRF_FLG Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 577 Internal. Only to be used through TI provided API. PROTL1DIS Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 578 Internal. Only to be used through TI provided API. 15-0 Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 579 Internal. Only to be used through TI provided API. BUSY Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 580 Internal. Only to be used through TI provided API. VREADS Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 581 Internal. Only to be used through TI provided API. BANKPWR0 Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 582 Internal. Only to be used through TI provided API. BANKRDY Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 583 Internal. Only to be used through TI provided API. PUMPPWR Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 584 Internal. Only to be used through TI provided API. 15-0 PAGP Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 585 Internal. Only to be used through TI provided API. BANK Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 586 Internal. Only to be used through TI provided API. SLOCK Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 587 Internal. Only to be used through TI provided API. 15-0 ENCOM 55AAh Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 588 Internal. Only to be used through TI provided API. VREADCT Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 589 Internal. Only to be used through TI provided API. VHVCT_PV Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 590 Internal. Only to be used through TI provided API. 15-0 RESERVED Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 591 Internal. Only to be used through TI provided API. VHVCT_READ Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 592 Internal. Only to be used through TI provided API. VIN_CT Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 593 Internal. Only to be used through TI provided API. 11-0 RESERVED Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 594 Internal. Only to be used through TI provided API. VWLCT_P Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 595 Internal. Only to be used through TI provided API. EFUSE_EN Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 596 Internal. Only to be used through TI provided API. SHIFT_DONE R/W1C Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 597 Table 7-54. FEFUSEDATA Register Field Descriptions Field Type Reset Description 31-0 FEFUSEDATA Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 598 Internal. Only to be used through TI provided API. SEQ_PUMP Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 599 Internal. Only to be used through TI provided API. RESERVED Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 600 Internal. Only to be used through TI provided API. V5PWRDNZ Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 601 Internal. Only to be used through TI provided API. MODE Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 602 Internal. Only to be used through TI provided API. Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 603 Table 7-60. FADDR Register Field Descriptions Field Type Reset Description 31-0 FADDR Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 604 Internal. Only to be used through TI provided API. RESERVED Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 605 Table 7-62. FWPWRITE0 Register Field Descriptions Field Type Reset Description 31-0 FWPWRITE0 FFFFFFFFh Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 606 Table 7-63. FWPWRITE1 Register Field Descriptions Field Type Reset Description 31-0 FWPWRITE1 FFFFFFFFh Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 607 Table 7-64. FWPWRITE2 Register Field Descriptions Field Type Reset Description 31-0 FWPWRITE2 FFFFFFFFh Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 608 Table 7-65. FWPWRITE3 Register Field Descriptions Field Type Reset Description 31-0 FWPWRITE3 FFFFFFFFh Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 609 Table 7-66. FWPWRITE4 Register Field Descriptions Field Type Reset Description 31-0 FWPWRITE4 FFFFFFFFh Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 610 Table 7-67. FWPWRITE5 Register Field Descriptions Field Type Reset Description 31-0 FWPWRITE5 FFFFFFFFh Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 611 Table 7-68. FWPWRITE6 Register Field Descriptions Field Type Reset Description 31-0 FWPWRITE6 FFFFFFFFh Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 612 Table 7-69. FWPWRITE7 Register Field Descriptions Field Type Reset Description 31-0 FWPWRITE7 FFFFFFFFh Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 613 Internal. Only to be used through TI provided API. ECCBYTES31_24 Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 614 Internal. Only to be used through TI provided API. SAFELV Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 615 Internal. Only to be used through TI provided API. CLKSEL Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 616 Internal. Only to be used through TI provided API. RESERVED Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 617 Internal. Only to be used through TI provided API. INV_DAT Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 618 Internal. Only to be used through TI provided API. FSMCMD Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 619 Internal. Only to be used through TI provided API. ERA_OSU Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 620 Internal. Only to be used through TI provided API. 11-0 RESERVED Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 621 Internal. Only to be used through TI provided API. ERA_VSU Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 622 Internal. Only to be used through TI provided API. 11-0 RESERVED Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 623 Internal. Only to be used through TI provided API. EXE_VALD Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 624 Internal. Only to be used through TI provided API. RD_H Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 625 Internal. Only to be used through TI provided API. RESERVED Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 626 Internal. Only to be used through TI provided API. 15-0 ERA_OH Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 627 Internal. Only to be used through TI provided API. 11-0 SAV_P_PUL Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 628 Internal. Only to be used through TI provided API. ERA_VH Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 629 Internal. Only to be used through TI provided API. 15-0 PROG_PUL_WIDTH Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 630 Table 7-87. FSM_ERA_PW Register Field Descriptions Field Type Reset Description 31-0 FSM_ERA_PW Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 631 Internal. Only to be used through TI provided API. 11-0 SAV_ERA_PUL Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 632 Table 7-89. FSM_TIMER Register Field Descriptions Field Type Reset Description 31-0 FSM_TIMER Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 633 Internal. Only to be used through TI provided API. Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 634 Internal. Only to be used through TI provided API. 22-0 PGM_ADDR Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 635 Internal. Only to be used through TI provided API. 22-0 ERA_ADDR Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 636 Internal. Only to be used through TI provided API. 11-0 MAX_PRG_PUL Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 637 Internal. Only to be used through TI provided API. 11-0 MAX_ERA_PUL BB8h Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 638 Internal. Only to be used through TI provided API. 15-0 RESERVED Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 639 Internal. Only to be used through TI provided API. 11-0 PUL_CNTR Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 640 Internal. Only to be used through TI provided API. EC_STEP_HEIGHT Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 641 Internal. Only to be used through TI provided API. OVERRIDE Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 642 Internal. Only to be used through TI provided API. BLK_OTP Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 643 Internal. Only to be used through TI provided API. WR_ENA Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 644 Table 7-101. FSM_ACC_PP Register Field Descriptions Field Type Reset Description 31-0 FSM_ACC_PP Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 645 Internal. Only to be used through TI provided API. 15-0 ACC_EP Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 646 Internal. Only to be used through TI provided API. 27-0 CUR_ADDR Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 647 Internal. Only to be used through TI provided API. SEC_OUT Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 648 Internal. Only to be used through TI provided API. 11-0 CONFIG_CRC Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 649 Internal. Only to be used through TI provided API. FSM_ERR_BANK Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 650 Internal. Only to be used through TI provided API. 11-0 FSM_PGM_MAXPUL Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 651 Internal. Only to be used through TI provided API. FSMEXECUTE Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 652 Table 7-109. FSM_SECTOR1 Register Field Descriptions Field Type Reset Description 31-0 FSM_SECTOR1 FFFFFFFFh Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 653 Table 7-110. FSM_SECTOR2 Register Field Descriptions Field Type Reset Description 31-0 FSM_SECTOR2 Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 654 Table 7-111. FSM_BSLE0 Register Field Descriptions Field Type Reset Description 31-0 FSM_BSLE0 Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 655 Table 7-112. FSM_BSLE1 Register Field Descriptions Field Type Reset Description 31-0 FSM_BSL1 Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 656 Table 7-113. FSM_BSLP0 Register Field Descriptions Field Type Reset Description 31-0 FSM_BSLP0 Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 657 Table 7-114. FSM_BSLP1 Register Field Descriptions Field Type Reset Description 31-0 FSM_BSL1 Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 658 Internal. Only to be used through TI provided API. MAIN_NUM_BANK Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 659 Internal. Only to be used through TI provided API. CPU_TYPE1 Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 660 Internal. Only to be used through TI provided API. B0_TYPE Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 661 Internal. Only to be used through TI provided API. 23-0 B0_START_ADDR Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 662 Internal. Only to be used through TI provided API. 23-0 B1_START_ADDR Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 663 Internal. Only to be used through TI provided API. 23-0 B2_START_ADDR Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 664 Internal. Only to be used through TI provided API. 23-0 B3_START_ADDR Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 665 Internal. Only to be used through TI provided API. 23-0 B4_START_ADDR Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 666 Internal. Only to be used through TI provided API. 23-0 B5_START_ADDR Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 667 Internal. Only to be used through TI provided API. 23-0 B6_START_ADDR Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 668 Internal. Only to be used through TI provided API. 23-0 B7_START_ADDR Internal. Only to be used through TI provided API. Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 669 Internal. Only to be used through TI provided API. B0_SECT_SIZE Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 670 Table 7-127. VIMS Registers Offset Acronym Register Name Section STAT Status Section 7.8.2.1 Control Section 7.8.2.2 Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 671 1h = CACHE : VIMS Cache mode 2h = VIMS Split Cache mode 3h = VIMS Off mode SWCU117C – February 2015 – Revised September 2015 Versatile Instruction Memory System (VIMS) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 672 1h = CACHE : VIMS Cache mode 2h = VIMS Split Cache mode 3h = VIMS Off mode Versatile Instruction Memory System (VIMS) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 673: Bootloader
SWCU117C – February 2015 – Revised September 2015 Bootloader This section describes the CC26xx and CC13xx bootloader..........................Topic Page ................... Bootloader Functionality ..................Bootloader Interfaces SWCU117C – February 2015 – Revised September 2015 Bootloader Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 674: Bootloader Functionality
The bootloader communicates with an external device over a 2-pin UART or a 4-pin SSI interface. The communication protocol and transport layers are described in the following sections. Bootloader SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 675: Packet Handling
4. Calculate the checksum of the data bytes and verify it matches the checksum received in the packet. 5. Send an acknowledge or not-acknowledge to the device to indicate the successful or unsuccessful reception of the packet. SWCU117C – February 2015 – Revised September 2015 Bootloader Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 676: Transport Layer
However, the UART0 requires fewer pins and can be easily implemented with any standard UART connection. Bootloader SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 677 3 Mbaud (48 MHz divided by 16). The maximum baud rate is restricted to 1.6 Mbaud because of the firmware function that detects the transfer rate of the host. SWCU117C – February 2015 – Revised September 2015 Bootloader Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 678: Serial Bus Commands
Table 8-4 for defined status values. The status is returned within a protocol packet of 3 bytes. 678 Bootloader SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 679 CCFG holding the defined CCFG fields. The following subsections specify the individual bytes within the protocol packets for each command. SWCU117C – February 2015 – Revised September 2015 Bootloader Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 680 = Program Address [7:0]; ucCommand[7] = Program Size [31:24]; ucCommand[8] = Program Size [23:16]; ucCommand[9] = Program Size [15:8]; ucCommand[10] = Program Size [7:0]; Bootloader SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 681 <checksum>; ucCommand[2]= COMMAND_ERASE; ucCommand[3]= Sector Address [31:24]; ucCommand[4]= Sector Address [23:16]; ucCommand[5]= Sector Address [15: 8]; ucCommand[6]= Sector Address [ 7: 0]; SWCU117C – February 2015 – Revised September 2015 Bootloader Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 682 The format of the packet including the command is as follows: unsigned char ucCommand[3]; ucCommand[0] = <size=3>; ucCommand[1] = <checksum>; ucCommand[2] = COMMAND_RESET; Bootloader SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 683 Read Repeat Count [31:24]; ucCommand[12]= Read Repeat Count [23:16]; ucCommand[13]= Read Repeat Count [15: 8]; ucCommand[14]= Read Repeat Count [7: 0]; SWCU117C – February 2015 – Revised September 2015 Bootloader Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 684 = Memory Map Address [15:8]; ucCommand[6] = Memory Map Address [7:0]; ucCommand[7] = Access Type [7:0]; ucCommand[8] = Number of Accesses [7:0]; Bootloader SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 685 = Memory Map Address [7:0]; ucCommand[7] = Access Type [7:0]; ucCommand[8] = Data [7:0]; ucCommand[9 + (packet size - 9)] = Data [7:0] or Data[31:24]; SWCU117C – February 2015 – Revised September 2015 Bootloader Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 686 = Field Id[15:8]; ucCommand[6] = Field Id[7:0]; ucCommand[7] = Field Value[31:24]; ucCommand[8] = Field Value[23:16]; ucCommand[9] = Field Value[15:8]; ucCommand[10] = Field Value[7:0]; Bootloader SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 687: Device Configuration
This chapter describes the device configuration areas. The factory configuration (FCFG) and customer configuration (CCFG) areas are located in flash. The FCFG is set by Texas Instruments during device production and contains device-specific trim values and configuration. The CCFG must be set by the application and contains configuration parameters for the ROM bootcode, device hardware, and device firmware.
Page 688: Customer Configuration (Ccfg)
CCFG_TAP_DAP_0:TEST_TAP_ENABLE register is not enabled in FCFG, the value in the corresponding CCFG field is ignored and the functionality is disabled. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 689: Ccfg Registers
FF4h CCFG_PROT_63_32 Protect Sectors 32-63 Section 9.1.1.20 FF8h CCFG_PROT_95_64 Protect Sectors 64-95 Section 9.1.1.21 FFCh CCFG_PROT_127_96 Protect Sectors 96-127 Section 9.1.1.22 SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 690 Unsigned integer, defining the input frequency of the external clock and is written to AON_RTC:SUBSECINC.VALUEINC. Defined as follows: EXT_LF_CLK.RTC_INCREMENT = 2 InputClockFrequency in Hertz (for example, RTC_INCREMENT=0x800000 for InputClockFrequency=32768 Hz) Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 691 See FCFG1:AMPCOMP_CTRL1.IBIAS_OFFSET XOSC_MAX_START Unsigned value of maximum XOSC start-up time (worst case) in units of 100 µs. Value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 692 (handled automatically if using TI RTOS). DIS_XOSC_OVR Disable XOSC override functionality. 0: Enable XOSC override functionality. 1: Disable XOSC override functionality. See: MODE_CONF_1.DELTA_IBIAS_INIT MODE_CONF_1.DELTA_IBIAS_OFFSET MODE_CONF_1.XOSC_MAX_START Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 693 PA output power on CC13xx). 1: VDDS BOD level is 1.8 V (or 1.65 V for external regulator mode) (default). SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 694 NOTE: If using the following functions this field must be configured (used by TI RTOS): SysCtrlSetRechargeBeforePowerDown() SysCtrlAdjustRechargeAfterPowerDown() Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 695 Reserved for future use. Software must not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 696 Reserved for future use. Software must not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 697 Reserved for future use. Software must not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 698 Reserved for future use. Software must not rely on the value of a reserved. Writing any other value than the reset/default value may result in undefined behavior. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 699 FFFFFFFFh Bits[31:0] of the 64-bits custom IEEE MAC address. If different from 0xFFFFFFFF, then the value of this field is applied; otherwise use the value from FCFG. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 700 FFFFFFFFh Bits[63:32] of the 64-bits custom IEEE MAC address. If different from 0xFFFFFFFF, then the value of this field is applied; otherwise use value from FCFG. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 701 FFFFFFFFh Bits [31:0] of the 64-bits custom IEEE BLE address. If different from 0xFFFFFFFF, then the value of this field is applied; otherwise use value from FCFG. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 702 FFFFFFFFh Bits [63:32] of the 64-bits custom IEEE BLE address. If different from 0xFFFFFFFF, then the value of this field is applied; otherwise use value from FCFG. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 703 Any other value: Boot loader backdoor is disabled. NOTE! Boot loader must be enabled (see BOOTLOADER_ENABLE) if boot loader backdoor is enabled. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 704 CCFG. 0: Disable the boot loader bank erase function. 1: Enable the boot loader bank erase function. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 705 Analysis) option with the unlock code. All other values: Disable the functionality of unlocking the TI FA option with the unlock code. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 706 ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI. Any other value: TEST TAP access will remain disabled out of power-up/system-reset. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 707 ROM boot FW if enabled by corresponding configuration value in FCFG1 defined by TI. Any other value: WUC TAP access will remain disabled out of power-up/system-reset. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 708 A nonzero value forces the boot sequence to call the boot loader. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 709 0: Sector protected WRT_PROT_SEC_15 0: Sector protected WRT_PROT_SEC_14 0: Sector protected WRT_PROT_SEC_13 0: Sector protected WRT_PROT_SEC_12 0: Sector protected WRT_PROT_SEC_11 0: Sector protected SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 710 0: Sector protected WRT_PROT_SEC_4 0: Sector protected WRT_PROT_SEC_3 0: Sector protected WRT_PROT_SEC_2 0: Sector protected WRT_PROT_SEC_1 0: Sector protected WRT_PROT_SEC_0 0: Sector protected Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 711 0: Sector protected WRT_PROT_SEC_47 0: Sector protected WRT_PROT_SEC_46 0: Sector protected WRT_PROT_SEC_45 0: Sector protected WRT_PROT_SEC_44 0: Sector protected WRT_PROT_SEC_43 0: Sector protected SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 712 0: Sector protected WRT_PROT_SEC_36 0: Sector protected WRT_PROT_SEC_35 0: Sector protected WRT_PROT_SEC_34 0: Sector protected WRT_PROT_SEC_33 0: Sector protected WRT_PROT_SEC_32 0: Sector protected Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 713 0: Sector protected WRT_PROT_SEC_79 0: Sector protected WRT_PROT_SEC_78 0: Sector protected WRT_PROT_SEC_77 0: Sector protected WRT_PROT_SEC_76 0: Sector protected WRT_PROT_SEC_75 0: Sector protected SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 714 0: Sector protected WRT_PROT_SEC_68 0: Sector protected WRT_PROT_SEC_67 0: Sector protected WRT_PROT_SEC_66 0: Sector protected WRT_PROT_SEC_65 0: Sector protected WRT_PROT_SEC_64 0: Sector protected Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 715 0: Sector protected WRT_PROT_SEC_111 0: Sector protected WRT_PROT_SEC_110 0: Sector protected WRT_PROT_SEC_109 0: Sector protected WRT_PROT_SEC_108 0: Sector protected WRT_PROT_SEC_107 0: Sector protected SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 716 0: Sector protected WRT_PROT_SEC_100 0: Sector protected WRT_PROT_SEC_99 0: Sector protected WRT_PROT_SEC_98 0: Sector protected WRT_PROT_SEC_97 0: Sector protected WRT_PROT_SEC_96 0: Sector protected Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 717: Factory Configuration (Fcfg)
Some of the more useful fields in FCFG are MAC_15_4_n fields, which give the preprogrammed IEEE address of the chipset, and the MAC_BLE_n fields that give the Bluetooth Smart address of the chipset. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 718: Fcfg1 Registers
2B4h ANA2_TRIM Misc Analog Trim Section 9.2.1.41 2B8h LDO_TRIM LDO Trim Section 9.2.1.42 2E8h MAC_BLE_0 MAC BLE Address 0 Section 9.2.1.43 Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 719 Power Down Current Control 95C Section 9.2.1.76 3B4h PWD_CURR_110C Power Down Current Control 110C Section 9.2.1.77 3B8h PWD_CURR_125C Power Down Current Control 125C Section 9.2.1.78 SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 720 Any test of this field by SW must be implemented as a 'greater or equal' comparison as signed integer. Value may change without warning. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 721 RFLDO_TRIM_OUTPUT Trim value for ADI_0_RF:RFLDO1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 722 RFLDO_TRIM_OUTPUT Trim value for ADI_0_RF:RFLDO1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 723 RFLDO_TRIM_OUTPUT Trim value for ADI_0_RF:RFLDO1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 724 RFLDO_TRIM_OUTPUT Trim value for ADI_0_RF:RFLDO1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 725 RFLDO_TRIM_OUTPUT Trim value for ADI_0_RF:RFLDO1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 726 RFLDO_TRIM_OUTPUT Trim value for ADI_0_RF:RFLDO1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 727 Value is read by RF Core ROM FW during RF Core initialization. SLDO_TRIM_OUTPUT Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 728 Value is read by RF Core ROM FW during RF Core initialization. SLDO_TRIM_OUTPUT Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 729 Value is read by RF Core ROM FW during RF Core initialization. SLDO_TRIM_OUTPUT Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 730 Value is read by RF Core ROM FW during RF Core initialization. SLDO_TRIM_OUTPUT Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 731 Value is read by RF Core ROM FW during RF Core initialization. SLDO_TRIM_OUTPUT Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 732 Value is read by RF Core ROM FW during RF Core initialization. SLDO_TRIM_OUTPUT Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 733 Value is read by RF Core ROM FW during RF Core initialization. DACTRIM Trim value for ADI_0_RF:IFADCDAC.TRIM. Value is read by RF Core ROM FW during RF Core initialization. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 734 Value is read by RF Core ROM FW during RF Core initialization. DACTRIM Trim value for ADI_0_RF:IFADCDAC.TRIM. Value is read by RF Core ROM FW during RF Core initialization. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 735 Value is read by RF Core ROM FW during RF Core initialization. DACTRIM Trim value for ADI_0_RF:IFADCDAC.TRIM. Value is read by RF Core ROM FW during RF Core initialization. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 736 Value is read by RF Core ROM FW during RF Core initialization. DACTRIM Trim value for ADI_0_RF:IFADCDAC.TRIM. Value is read by RF Core ROM FW during RF Core initialization. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 737 Value is read by RF Core ROM FW during RF Core initialization. DACTRIM Trim value for ADI_0_RF:IFADCDAC.TRIM. Value is read by RF Core ROM FW during RF Core initialization. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 738 Value is read by RF Core ROM FW during RF Core initialization. DACTRIM Trim value for ADI_0_RF:IFADCDAC.TRIM. Value is read by RF Core ROM FW during RF Core initialization. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 739 Table 9-44. SHDW_DIE_ID_0 Register Field Descriptions Field Type Reset Description 31-0 ID_31_0 Shadow of EFUSE:DIE_ID_0, ie efuse row number 3 Default value depends on eFuse value. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 740 Table 9-45. SHDW_DIE_ID_1 Register Field Descriptions Field Type Reset Description 31-0 ID_63_32 Shadow of EFUSE:DIE_ID_1, ie efuse row number 4 Default value depends on eFuse value. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 741 Table 9-46. SHDW_DIE_ID_2 Register Field Descriptions Field Type Reset Description 31-0 ID_95_64 Shadow of EFUSE:DIE_ID_2, ie efuse row number 5 Default value depends on eFuse value. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 742 Table 9-47. SHDW_DIE_ID_3 Register Field Descriptions Field Type Reset Description 31-0 ID_127_96 Shadow of EFUSE:DIE_ID_3, ie efuse row number 6 Default value depends on eFuse value. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 743 Default value depends on eFuse value. RCOSCHF_CTRIM Shadow of EFUSE:OSC_BIAS_LDO_TRIM.RCOSCHF_CTRIM, ie in efuse row number 11 Default value depends on eFuse value. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 744 Default value depends on eFuse value. TRIMTEMP Shadow of EFUSE:ANA_TRIM.TRIMTEMP, ie in efuse row number Default value depends on eFuse value. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 745 Reset Description 31-0 LOT_NUMBER Number of the manufacturing lot that produced this unit. Default value holds log information from production test. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 746 Default value holds log information from production test. 15-0 YCOORDINATE Y coordinate of this unit on the wafer. Default value holds log information from production test. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 747 Erase verify setup time in cycles. Value will be written to FLASH:FSM_PE_VSU.ERA_VSU by the flash device driver when an erase/program operation is initiated. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 748 Address->EXECUTEZ setup time in cycles. Value will be written to FLASH:FSM_CMP_VSU.ADD_EXZ by the flash device driver when an erase/program operation is initiated.. 11-0 CVSU Compaction verify setup time in cycles. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 749 FLASH:FSM_PE_VH.PGM_VH when an erase/program operation is initiated. PVH2 Program verify row switch time in half-microseconds. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 750 FLASH:FSM_VSTAT.VSTAT_CNT when an erase/program operation is initiated. 11-0 SM_FREQUENCY Max FCLK frequency allowed for program, erase, and verify reads. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 751 The actual FMC register value must be one less than this since the FMC starts counting from zero. Value will be written to FLASH:FSM_EC_STEP_HEIGHT.EC_STEP_HEIGHT when an erase/program operation is initiated. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 752 15-0 MAX_PP Max program pulse limit per program operation. Value will be written to FLASH:FSM_PRG_PUL.MAX_PRG_PUL when an erase/program operation is initiated. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 753 FCLK cycles by the flash device driver and the converted value is written to FLASH:FSM_PRG_PW.PROG_PUL_WIDTH when a erase/program operation is initiated. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 754 FCLK cycles by the flash device driver and the converted value is written to FLASH:FSM_ERA_PW.FSM_ERA_PW when a erase/program operation is initiated. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 755 VHV_E Value will be written to FLASH:FVHVCT1.VHVCT_E by the flash device driver when an erase/program operation is initiated SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 756 Default value holds trim value from production test. VINH Inhibit voltage applied to unselected columns during programming. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 757 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Default value holds trim value from production test. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 758 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Default value differs depending on partnumber. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 759 FLASH:CFG.CONFIGURED. Default value differs depending on partnumber. WAIT_SYSCODE Value will be written to FLASH:WAIT_SYSCODE.WAIT_SYSCODE by boot FW code while in safezone. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 760 Value will be written to ADI_3_REFSYS:DCDCCTL4.DEADTIME_TRIM by boot FW while in safezone. DCDC_LOW_EN_SEL Value will be written to ADI_3_REFSYS:DCDCCTL4.LOW_EN_SEL by boot FW while in safezone. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 761 Table 9-65. ANA2_TRIM Register Field Descriptions (continued) Field Type Reset Description DCDC_HIGH_EN_SEL Value will be written to ADI_3_REFSYS:DCDCCTL4.HIGH_EN_SEL by boot FW while in safezone. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 762 VTRIM_DELTA Value will be written to ADI_2_REFSYS:SOCLDOCTL2.VTRIM_DELTA by boot FW while in safezone. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 763 Reset Description 31-0 ADDR_0_31 The first 32-bits of the 64-bit MAC BLE address Default value holds trim value from production test. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 764 Reset Description 31-0 ADDR_32_63 The last 32-bits of the 64-bit MAC BLE address Default value holds trim value from production test. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 765 Reset Description 31-0 ADDR_0_31 The first 32-bits of the 64-bit MAC 15.4 address Default value holds trim value from production test. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 766 Reset Description 31-0 ADDR_32_63 The last 32-bits of the 64-bit MAC 15.4 address Default value holds trim value from production test. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 767 If AON_SYSCTL:PWRCTL.EXT_REG_MODE = 1, this value will be written to FLASH:CFG.DIS_IDLE by flash device driver FW when a flash write operation is initiated. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 768 FLASH:FSEQPMP.VIN_AT_X both by boot FW while in safezone, and by flash device driver FW after completion of a flash write operation. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 769 TEMPVSLOPE Signed byte value representing the TEMP slope with battery voltage, in degrees C / V, with four fractional bits. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 770 Change in CTRIM trim 15-8 CTRIMFRACT_QUAD Temp compensation quadratic CTRIMFRACT CTRIMFRACT_SLOPE Number of CTRIMFRACT codes per 20 degrees C from default temperature Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 771 Field used to distinguish revisions of the device. 27-12 WAFER_ID B99Ah Field used to identify silicon die. 11-0 MANUFACTURER_ID Manufacturer code. 0x02F: Texas Instruments SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 772 FCFG1 layout has changed since the previous production of devices. Value migth change without warning. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 773 The revision of the test program used in the production process when FCFG1 was programmed. Value migth change without warning. Default value holds log information from production test. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 774 GPIO_CNT This value is written to IOC:CFG.GPIO_CNT by boot FW while in safezone. Default value differs depending on partnumber. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 775 Trim value for ADI_0_RF:IFALDO2.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. Default value holds trim value from production test. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 776 DDI_0_OSC:ANABYPASSVAL1.XOSC_HF_COLUMN_Q12. RCOSCLF_CTUNE_TRIM R Trim value for DDI_0_OSC:LFOSCCTL.RCOSCLF_CTUNE_TRIM. Default value holds trim value from production test. RCOSCLF_RTUNE_TRIM R Trim value for DDI_0_OSC:LFOSCCTL.RCOSCLF_RTUNE_TRIM. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 777 Trim value for ADI_0_RF:RFLDO1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. Default value holds trim value from production test. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 778 Trim value for ADI_1_SYNTH:SLDOCTL1.TRIM_OUT. Value is read by RF Core ROM FW during RF Core initialization. Default value holds trim value from production test. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 779 SOC_ADC gain in absolute reference mode at temperature 1 (30C). EMP1 Calculated in production test.. Default value holds log information from production test. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 780 SOC_ADC gain in relative reference mode at temperature 1 (30C). EMP1 Calculated in production test.. Default value holds trim value from production test. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 781 SOC_ADC offset in absolute reference mode at temperature 1 T_TEMP1 (30C). Signed 8-bit number. Calculated in production test.. Default value holds trim value from production test. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 782 SOC_ADC_REF_VOLTA Value to write in ADI_4_AUX:ADCREF1.VTRIM at temperature 1 GE_TRIM_TEMP1 (30C). Default value holds trim value from production test. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 783 IBIAS and CAP trim open loop count. CAP_REM is remainder of the CAP that is left to reach the final cap value. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 784 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 785 CAP_TRIM = CAP_INIT - CAP_STEP*IBIASCAP_HPTOLP_OL_CNT - CAP_REM IBIAS_TRIM = IBIAS_INIT - 1*IBIASCAP_HPTOLP_OL_CNT Here, cap_init is decimal conversion of cap_init_col and cap_init_row. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 786 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. 13-0 XOSC_HF_IBIASTHERM 3FFh Value of xosc_hf_ibiastherm when oscdig is bypassed. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 787 Value is read by RF Core ROM FW during RF Core initialization. DACTRIM Trim value for ADI_0_RF:IFADCDAC.TRIM. Value is read by RF Core ROM FW during RF Core initialization. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 788 TRIMBOD_H Trim value for 2.0V VDDS BOD target found in production test. Default value holds trim value from production test. Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 789 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. Default value holds trim value from production test. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 790 CAP (measured in production test) 15-0 FLUX_CAP_0P4_TRIM FFFFh Reserved storage of measurement value on 0.4um pitch FLUX CAP (measured in production test) Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 791 Trim value for ESET_VOLTAGE DDI_0_OSC:ADCDOUBLERNANOAMPCTL.DBLR_LOOP_FILTER_ RESET_VOLTAGE. 19-10 HPM_IBIAS_WAIT_CNT 100h Trim value for DDI_0_OSC:RADCEXTCFG.HPM_IBIAS_WAIT_CNT. LPM_IBIAS_WAIT_CNT Trim value for DDI_0_OSC:RADCEXTCFG.LPM_IBIAS_WAIT_CNT. IDAC_STEP Trim value for DDI_0_OSC:RADCEXTCFG.IDAC_STEP. SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 792 Additional maximum current, in units of 1 µA, with XOSC_HF on in low-power mode BASELINE Worst-case baseline maximum power-down current, in units of 0.5 µA Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 793 Additional maximum current, in units of 1 µA, with XOSC_HF on in low-power mode BASELINE Worst-case baseline maximum power-down current, in units of 0.5µA SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 794 Additional maximum current, in units of 1 µA, with XOSC_HF on in low-power mode BASELINE Worst-case baseline maximum power-down current, in units of 0.5 µA Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 795 Additional maximum current, in units of 1 µA, with XOSC_HF on in low-power mode BASELINE Worst-case baseline maximum power-down current, in units of 0.5 µA SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 796 Additional maximum current, in units of 1 µA, with XOSC_HF on in low-power mode BASELINE Worst-case baseline maximum power-down current, in units of 0.5 µA Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 797 Additional maximum current, in units of 1 µA, with XOSC_HF on in low-power mode BASELINE Worst-case baseline maximum power-down current, in units of 0.5 µA SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 798 Additional maximum current, in units of 1 µA, with XOSC_HF on in low-power mode BASELINE Worst-case baseline maximum power-down current, in units of 0.5 µA Device Configuration SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 799 Additional maximum current, in units of 1 µA, with XOSC_HF on in low-power mode BASELINE Worst-case baseline maximum power-down current, in units of 0.5 µA SWCU117C – February 2015 – Revised September 2015 Device Configuration Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 800: Cryptography
128-bit key support, local key storage, and DMA capability. This chapter provides the description and information for configuring the AES engine..........................Topic Page ................. 10.1 AES Cryptoprocessor Overview ..................10.2 Cryptography Registers Cryptography SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 801: Aes Cryptoprocessor Overview
When a block is preloaded, the previous block must finish before additional data can be loaded. Therefore, once the pipeline is full, sequential data blocks can be passed every 32 clock cycles. SWCU117C – February 2015 – Revised September 2015 Cryptography Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 802: Power Management And Sleep Modes
DMA request, the first write transfer is an IDLE transfer. The last transfer is always an IDLE transfer. Cryptography SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 803: Module Description
Section 10.2.1.2 address 0x4002 400C DMACH0LEN 0x0000 0000 Channel 0 DMA Section 10.2.1.3 length 0x4002 4018 DMASTAT 0x0000 0000 DMAC status Section 10.2.1.4 SWCU117C – February 2015 – Revised September 2015 Cryptography Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 804 0x4002 4704 DMAPROTCTL 0x0000 0000 Enable privileged Section 10.2.1.33 access on master 0x4002 4740 SWRESET 0x0000 0000 Master-control Section 10.2.1.34 software reset 804 Cryptography SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 805 The DMAC of the AES module controls the data transfer requests to the AHB master adapter, which transfers data to and from the AES engines and key store area. SWCU117C – February 2015 – Revised September 2015 Cryptography Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 806 NOTE: The internal destination is programmed using a dedicated algorithm selection register in master control module. The burst size is provided to the DMAC based on the setting of that register. Cryptography SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 807 TAG is transferred through the slave interface or transferred with a separate DMA. Data is transferred through another DMA, that has been executed before. SWCU117C – February 2015 – Revised September 2015 Cryptography Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 808 The DMAC waits for the existing (active) requests to finish, then sets the DMAC status registers. Cryptography SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 809 When a decryption key is generated, subsequent decryption operations with the same key use this generated decryption key directly. SWCU117C – February 2015 – Revised September 2015 Cryptography Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 810 10.1.4.5.2 AES Initialization Vector (IV) Registers Table 10-6 shows the AES Initialization Vector registers that are used to provide and read the IV from the AES engine. Cryptography SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 811 When writing a new mode without writing the length registers, the values of the length register from the previous context are reused. SWCU117C – February 2015 – Revised September 2015 Cryptography Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 812 CCM decrypt data n-bit ciphertext block n-bit plaintext block CBC-MAC data n-bit plaintext block no output data SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 813 Trying to write to a key area that already contains a valid key is not allowed and results in an error. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 814: Performance
For longer data streams, the data processing time approaches the theoretical maximum throughput. For operations that use the slave interface as alternative for the DMA, the performance depends on the performance of the host CPU. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 815: Programming Guidelines
DMA operations. 3. Initialize the desired interrupt type (level), and enable the interrupt output signal RESULT_AVAIL in the master control module. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 816 Therefore, to correctly recover the engine, the master control soft reset must be issued by the SWRESET register after all active DMAC channels are stopped. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 817 Result data must be read using the same interface as the input data: either using the slave interface or DMA. • The result tag for operations with authentication can be read using the slave interface or DMA. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 819 If the result IV must be read by the host, the save_context bit must be set to 1 after processing the programmed number of bytes. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 820 AESCTL[30]==’1’ // wait for SAVED_CONTEXT_RDY bit [30] read AESIV_0 read AESIV_3 // this read clears the SAVED_CONTEXT_RDY flag endif // end of algorithm SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 821 A new data stream must always write the complete context. The length field must never be written with zeroes. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 822 AESCTL[30]==’1’ // wait for the SAVED_CONTEXT_RDY bit [30] read AESTAGOUT__0 - AESTAGOUT__3 // this read clears the SAVED_CONTEXT_RDY flag // end of algorithm SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 823 AESDATALEN0// write the length of the crypto block (lo) write AESDATALEN1// write the length of the crypto block (hi) // (may be non-block size aligned) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 824 AESCTL[30]==’1‘ // wait for the SAVED_CONTEXT_RDY bit [30] read AESTAGOUT__0 - AESTAGOUT__3 // this read clears the ‘saved_context_ready’ flag // end of algorithm SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 825 NOTE: In case of a read error, the key store writes a key with all bytes set to 0 to the AES engine. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 826: Conventions And Compliances
Most Significant Word Operating System Request for Comments SPRAM Single Port Random Access Memory SRAM Static Random Access Memory Tightly Coupled Memory (memory interface protocol) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 827 31:0 indicates a size of 32 bits with most significant bit 31 and least significant bit 0. 11:3 indicates a size of 9 bits with most significant bit 11 and least significant bit 3. 10.1.7.2 Compliances AES encryption in ECB and CBC modes complies with FIPS-197. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 828: Cryptography Registers
Interrupt Clear Section 10.2.1.37 78Ch IRQSET Interrupt Set Section 10.2.1.38 790h IRQSTAT Interrupt Status Section 10.2.1.39 7FCh HWVER CTRL Module Version Section 10.2.1.40 SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 829 Round Robin scheme. 0h = Priority low 1h = Priority high DMA Channel 0 Control 0h = Channel disabled 1h = Channel enabled SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 830 Field Type Reset Description 31-0 ADDR Channel external address value. Holds the last updated external address after being sent to the master interface. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 831 DMA transfer length after being sent to the master interface. Note: Writing a nonzero value to this register field starts the transfer if the channel is enabled by setting DMACH0CTL.EN. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 832 0: Not active 1: Active CH0_ACTIVE This register field indicates if DMA channel 0 is active or not. 0: Not active 1: Active SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 833 Software reset enable 0: Disable 1: Enable (self-cleared to zero). Note: Completion of the software reset must be checked in DMASTAT.CH0_ACTIVE and DMASTAT.CH1_ACTIVE. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 834 Note: Disabling an active channel will interrupt the DMA operation. The ongoing block transfer will be completed, but no new transfers will be requested. 0h = Channel disabled 1h = Channel enabled SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 835 Field Type Reset Description 31-0 ADDR Channel external address value. Holds the last updated external address after being sent to the master interface. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 836 DMA transfer length after being sent to the master interface. Note: Writing a nonzero value to this register field starts the transfer if the channel is enabled by setting DMACH1CTL.EN. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 837 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 838 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 839 Minor version number 19-16 HW_PATCH_LVL Patch level 15-8 VER_NUM_COMPL Bit-by-bit complement of the VER_NUM field bits VER_NUM Version number of the DMA Controller (209) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 840 RAM areas are sequential. 0h = This RAM area is not selected to be written. 1h = This RAM area is selected to be written. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 841 RAM areas are sequential. 0h = This RAM area is not selected to be written . 1h = This RAM area is selected to be written. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 842 0h = This RAM area is not written with valid key information. 1h = This RAM area is written with valid key information. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 843 0h = This RAM area is not written with valid key information. 1h = This RAM area is written with valid key information. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 844 KEYWRITTENAREA will be reset when writing to this register. 1h = 128_BIT : 128 bits 2h = 192_BIT : Not supported 3h = 256_BIT : Not supported SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 845 4h = RAM Area 4 5h = RAM Area 5 6h = RAM Area 6 7h = RAM Area 7 8h = No RAM SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 846 = 0, 32, 64, 96 ordered from the LSW entry of this 4-deep register array. The interpretation of this field depends on the crypto operation mode. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 847 = 0, 32, 64, 96 ordered from the LSW entry of this 4-deep register arrary. The interpretation of this field depends on the crypto operation mode. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 848 Table 10-28. AESIV_0 to AESIV_3 Register Field Descriptions Field Type Reset Description 31-0 The interpretation of this field depends on the crypto operation mode. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 849 Defines L that indicates the width of the length field for CCM operations. The length field in bytes equals the value of CMM_L plus one. All values are supported. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 850 For typical use, this bit does NOT need to be written, but is used for status reading only. In this case, this status bit is automatically maintained by the Crypto peripheral. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 851 Description 31-0 LEN_LSW Used to write the Length values to the Crypto peripheral. This register contains bits [31:0] of the combined data length. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 852 Crypto peripheral. For block cipher modes, the data length must be programmed in multiples of the block cipher size, 16 bytes. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 853 Once processing with this context is started, this length decrements to zero. Writing this register triggers the engine to start using this context for CCM. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 854 (message) bytes/words can be written with any data. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 855 GCM, CCM and CBC- MAC. For CTR mode, the remaining data in an unaligned data block is ignored. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 856 (message) bytes/words can be written with any data. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 857 GCM, CCM and CBC- MAC. For CTR mode, the remaining data in an unaligned data block is ignored. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 858 (message) bytes/words can be written with any data. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 859 GCM, CCM and CBC- MAC. For CTR mode, the remaining data in an unaligned data block is ignored. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 860 (message) bytes/words can be written with any data. Note: The AAD / authentication only data is not copied to the output buffer but only used for authentication. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 861 GCM, CCM and CBC- MAC. For CTR mode, the remaining data in an unaligned data block is ignored. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 862 Table 10-41. AESTAGOUT_0 to AESTAGOUT_3 Register Field Descriptions Field Type Reset Description 31-0 This register contains the authentication TAG for the combined and authentication-only modes. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 863 If set to 1, selects the Key Store to be loaded through DMA. The maximum transfer size to DMA engine is set to 32 bytes (however transfers of 16, 24 and 32 bytes are allowed) SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 864 Select AHB transfer protection control for DMA transfers using the key store area as destination. 0 : Transfers use USER-type access. 1 : Transfers use PRIVILEGED-type access. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 865 Writing 0 has no effect. The bit is self cleared after executing the reset. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 866 Interrupt enable. This bit must be set to 1 to enable interrupts from the Crypto peripheral. 0 : All interrupts are disabled enabled. 1 : All interrupts are enabled. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 867 DMA_IN_DONE This bit enables IRQSTAT.DMA_IN_DONE as source for IRQ. RESULT_AVAIL This bit enables IRQSTAT.RESULT_AVAIL as source for IRQ. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 868 DMA_IN_DONE If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is cleared. RESULT_AVAIL If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is cleared. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 869 If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is set. Writing 0 has no effect. RESULT_AVAIL If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is set. Writing 0 has no effect. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 870 This bit returns the status of DMA data in done interrupt. RESULT_AVAIL This bit is set high when the Crypto peripheral has a result available. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 871 Crypto peripheral register is indeed read. VER_NUM The version number for the Crypto peripheral, this field contains the value 120 (decimal) or 0x78. SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 872: I/O Control
....................... 11.7 GPIO ....................11.8 I/O Pin Mapping ..................11.9 Peripheral PORTIDs ......................11.10 I/O Pin ..................11.11 I/O Control Registers I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 873 Pins AON IOC Peripherals AON PERIPH AON Peripherals oe_n AON/AUX MUX TMS CTRL TMS Pin Latch bmon_level DEBUG SS AON BATMON SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 874: I/O Mapping And Configuration
PA enable RFC_GPO2 0x31 RF Core Data Out 2 TX start RFC_GPO3 0x32 RF Core Data Out 3 Synth calibration running I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 875: Map 32-Khz System Clock (Lf Clock) To Dio/Pin
AUX domain. There are more constraints and reliability issues to consider before powering off a domain; (for more details, refer to Section 17.5, Power Management). SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 876: Unused I/O Pins
4. Toggle the DIO1 output by issuing an XOR operation on the GPIO:DOUT3_0:DIO1 bit with 0x100. 5. Call the following driver library functions: IOCPinTypeGpioOutput(0x1); GPIOPinToggle(0x1); I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 877: I/O Pin Mapping
2 mA / 4 mA 2 mA / 4 mA 2 mA / 4 mA 2 mA / 4 mA CC13xx does not have DIO0. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 878: Peripheral Portids
11-2, which gives a rough overview of the analog pin stage. Pullup and pulldown resistances are given in the data sheet. I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 879: Pin Configuration
Enables or disables the I/O input driver. • Output Driver (Depends on specific peripheral mapped to pin) Enables or disables the I/O output driver. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 880: I/O Control Registers
Section 11.11.1.2 IOSTRMAX IO Drive Strength Maximum Section 11.11.1.3 IOCLATCH IO Latch Control Section 11.11.1.4 CLK32KCTL SCLK_LF External Output Control Section 11.11.1.5 I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 881 31-3 RESERVED Internal. Only to be used through TI provided API. GRAY_CODE Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 882 31-3 RESERVED Internal. Only to be used through TI provided API. GRAY_CODE Internal. Only to be used through TI provided API. I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 883 31-3 RESERVED Internal. Only to be used through TI provided API. GRAY_CODE Internal. Only to be used through TI provided API. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 884 1h = Latches are transparent, meaning the value of the IO is directly controlled by the GPIO or peripheral value I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 885 0: Output enable active. SCLK_LF output on IO pin that has PORT_ID (e.g. IOC:IOCFG0.PORT_ID) set to AON_CLK32K. 1: Output enable not active SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 886: Gpio Registers
DOE31_0 Data Output Enable for DIO 0 to 31 Section 11.11.2.14 EVFLAGS31_0 Event Register for DIO 0 to 31 Section 11.11.2.15 I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 887 DIO0 Sets the state of the pin that is configured as DIO 0, if the corresponding DOE31_0 bit field is set. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 888 DIO4 Sets the state of the pin that is configured as DIO 4, if the corresponding DOE31_0 bit field is set. I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 889 DIO8 Sets the state of the pin that is configured as DIO 8, if the corresponding DOE31_0 bit field is set. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 890 DIO12 Sets the state of the pin that is configured as DIO 12, if the corresponding DOE31_0 bit field is set. I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 891 DIO16 Sets the state of the pin that is configured as DIO 16, if the corresponding DOE31_0 bit field is set. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 892 DIO20 Sets the state of the pin that is configured as DIO 20, if the corresponding DOE31_0 bit field is set. I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 893 DIO24 Sets the state of the pin that is configured as DIO 24, if the corresponding DOE31_0 bit field is set. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 894 DIO28 Sets the state of the pin that is configured as DIO 28, if the corresponding DOE31_0 bit field is set. I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 895 Data output for DIO 10 DIO9 Data output for DIO 9 DIO8 Data output for DIO 8 DIO7 Data output for DIO 7 SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 896 Data output for DIO 3 DIO2 Data output for DIO 2 DIO1 Data output for DIO 1 DIO0 Data output for DIO 0 I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 897 Set bit 13 DIO12 Set bit 12 DIO11 Set bit 11 DIO10 Set bit 10 DIO9 Set bit 9 DIO8 Set bit 8 SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 898 Set bit 5 DIO4 Set bit 4 DIO3 Set bit 3 DIO2 Set bit 2 DIO1 Set bit 1 DIO0 Set bit 0 I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 899 Clears bit 13 DIO12 Clears bit 12 DIO11 Clears bit 11 DIO10 Clears bit 10 DIO9 Clears bit 9 DIO8 Clears bit 8 SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 900 Clears bit 5 DIO4 Clears bit 4 DIO3 Clears bit 3 DIO2 Clears bit 2 DIO1 Clears bit 1 DIO0 Clears bit 0 I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 901 Toggles bit 13 DIO12 Toggles bit 12 DIO11 Toggles bit 11 DIO10 Toggles bit 10 DIO9 Toggles bit 9 DIO8 Toggles bit 8 SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 902 Toggles bit 5 DIO4 Toggles bit 4 DIO3 Toggles bit 3 DIO2 Toggles bit 2 DIO1 Toggles bit 1 DIO0 Toggles bit 0 I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 903 Data input from DIO 10 DIO9 Data input from DIO 9 DIO8 Data input from DIO 8 DIO7 Data input from DIO 7 SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 904 Data input from DIO 3 DIO2 Data input from DIO 2 DIO1 Data input from DIO 1 DIO0 Data input from DIO 0 I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 905 DIO9 Data output enable for DIO 9 DIO8 Data output enable for DIO 8 DIO7 Data output enable for DIO 7 SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 906 DIO2 Data output enable for DIO 2 DIO1 Data output enable for DIO 1 DIO0 Data output enable for DIO 0 I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 907 Event for DIO 13 DIO12 R/W1C Event for DIO 12 DIO11 R/W1C Event for DIO 11 DIO10 R/W1C Event for DIO 10 SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 908 Event for DIO 3 DIO2 R/W1C Event for DIO 2 DIO1 R/W1C Event for DIO 1 DIO0 R/W1C Event for DIO 0 I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 909: Ioc Registers
Configuration of DIO28 Section 11.11.3.29 IOCFG29 Configuration of DIO29 Section 11.11.3.30 IOCFG30 Configuration of DIO30 Section 11.11.3.31 IOCFG31 Configuration of DIO31 Section 11.11.3.32 SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 910 5h = OPENDR_INV : Open Drain Inverted input/output 6h = OPENSRC : Open Source Normal input/output 7h = OPENSRC_INV : Open Source Inverted input/output I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 911 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 912 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 913 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 914 5h = OPENDR_INV : Open Drain Inverted input/output 6h = OPENSRC : Open Source Normal input/output 7h = OPENSRC_INV : Open Source Inverted input/output I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 915 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 916 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 917 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 918 5h = OPENDR_INV : Open Drain Inverted input/output 6h = OPENSRC : Open Source Normal input/output 7h = OPENSRC_INV : Open Source Inverted input/output I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 919 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 920 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 921 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 922 5h = OPENDR_INV : Open Drain Inverted input/output 6h = OPENSRC : Open Source Normal input/output 7h = OPENSRC_INV : Open Source Inverted input/output I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 923 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 924 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 925 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 926 5h = OPENDR_INV : Open Drain Inverted input/output 6h = OPENSRC : Open Source Normal input/output 7h = OPENSRC_INV : Open Source Inverted input/output I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 927 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 928 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 929 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 930 5h = OPENDR_INV : Open Drain Inverted input/output 6h = OPENSRC : Open Source Normal input/output 7h = OPENSRC_INV : Open Source Inverted input/output I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 931 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 932 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 933 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 934 5h = OPENDR_INV : Open Drain Inverted input/output 6h = OPENSRC : Open Source Normal input/output 7h = OPENSRC_INV : Open Source Inverted input/output I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 935 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 936 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 937 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 938 5h = OPENDR_INV : Open Drain Inverted input/output 6h = OPENSRC : Open Source Normal input/output 7h = OPENSRC_INV : Open Source Inverted input/output I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 939 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 940 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 941 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 942 5h = OPENDR_INV : Open Drain Inverted input/output 6h = OPENSRC : Open Source Normal input/output 7h = OPENSRC_INV : Open Source Inverted input/output I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 943 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 944 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 945 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 946 5h = OPENDR_INV : Open Drain Inverted input/output 6h = OPENSRC : Open Source Normal input/output 7h = OPENSRC_INV : Open Source Inverted input/output I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 947 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 948 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 949 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 950 5h = OPENDR_INV : Open Drain Inverted input/output 6h = OPENSRC : Open Source Normal input/output 7h = OPENSRC_INV : Open Source Inverted input/output I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 951 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 952 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 953 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 954 5h = OPENDR_INV : Open Drain Inverted input/output 6h = OPENSRC : Open Source Normal input/output 7h = OPENSRC_INV : Open Source Inverted input/output I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 955 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 956 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 957 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 958 5h = OPENDR_INV : Open Drain Inverted input/output 6h = OPENSRC : Open Source Normal input/output 7h = OPENSRC_INV : Open Source Inverted input/output I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 959 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 960 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 961 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 962 5h = OPENDR_INV : Open Drain Inverted input/output 6h = OPENSRC : Open Source Normal input/output 7h = OPENSRC_INV : Open Source Inverted input/output I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 963 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 964 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 965 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 966 5h = OPENDR_INV : Open Drain Inverted input/output 6h = OPENSRC : Open Source Normal input/output 7h = OPENSRC_INV : Open Source Inverted input/output I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 967 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 968 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 969 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 970 5h = OPENDR_INV : Open Drain Inverted input/output 6h = OPENSRC : Open Source Normal input/output 7h = OPENSRC_INV : Open Source Inverted input/output I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 971 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 972 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 973 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 974 5h = OPENDR_INV : Open Drain Inverted input/output 6h = OPENSRC : Open Source Normal input/output 7h = OPENSRC_INV : Open Source Inverted input/output I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 975 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 976 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 977 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 978 5h = OPENDR_INV : Open Drain Inverted input/output 6h = OPENSRC : Open Source Normal input/output 7h = OPENSRC_INV : Open Source Inverted input/output I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 979 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 980 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 981 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 982 5h = OPENDR_INV : Open Drain Inverted input/output 6h = OPENSRC : Open Source Normal input/output 7h = OPENSRC_INV : Open Source Inverted input/output I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 983 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 984 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 985 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 986 5h = OPENDR_INV : Open Drain Inverted input/output 6h = OPENSRC : Open Source Normal input/output 7h = OPENSRC_INV : Open Source Inverted input/output I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 987 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 988 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 989 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 990 5h = OPENDR_INV : Open Drain Inverted input/output 6h = OPENSRC : Open Source Normal input/output 7h = OPENSRC_INV : Open Source Inverted input/output I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 991 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 992 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 993 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 994 5h = OPENDR_INV : Open Drain Inverted input/output 6h = OPENSRC : Open Source Normal input/output 7h = OPENSRC_INV : Open Source Inverted input/output I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 995 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 996 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 997 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 998 5h = OPENDR_INV : Open Drain Inverted input/output 6h = OPENSRC : Open Source Normal input/output 7h = OPENSRC_INV : Open Source Inverted input/output I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 999 Software must not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. SWCU117C – February 2015 – Revised September 2015 I/O Control Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...
Page 1000 21h = SSI1_RX : SSI1 RX 22h = SSI1_TX : SSI1 TX 23h = SSI1_FSS : SSI1 FSS 24h = SSI1_CLK : SSI1 CLK 1000 I/O Control SWCU117C – February 2015 – Revised September 2015 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated...

This manual is also suitable for:

Simplelink cc2650 Simplelink cc1310 Simplelink cc2630 Simplelink cc2640

Texas Instruments SimpleLink CC2620 Technical Reference Manual

Quick Links

Related Manuals for Texas Instruments SimpleLink CC2620

Summary of Contents for Texas Instruments SimpleLink CC2620

This manual is also suitable for: