Texas Instruments SimpleLink CC2620 Technical Reference Manual page 421

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6.1.4.2 Clocks in MCU_VD
AON_WUC supports MCU_VD with a clock that is divided and gated by PRCM before being distributed to
all modules in MCU_VD.
all module clocks. When no BUS transactions can occur, hardware automatically gates the SYSBUS
clock.
The following conditions must be true to gate the SYSBUS:
• System CPU in deepsleep mode
• PRCM:SECDMACLKGDS.DMA_CLK_EN = 0
• PRCM:SECDMACLKGDS.SEC_CLK_EN = 0
• RFCORE FW does not require bus access
The SYSBUS clock may run even when the system CPU is in deepsleep mode when either DMA, SEC, or
RFCORE needs an active interconnect.
MCU_AON has two clocks, an INFRASTRUCTURE clock that always runs and a PERBUSULL clock that
is identical to the INFRASTRUCTURE clock whenever the SYSBUS clock is running. When the SYSBUS
clock is gated, the PERBUSULL clock is automatically gated. INFRASTRUCTURE and PERBUSULL
clocks are automatically controlled to run at a maximum of half the clock frequency of SCLK_HF,
regardless of the settings in PRCM:INFCLKDIVR/S/DS.
SWCU117C – February 2015 – Revised September 2015
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Figure 6-6 shows the registers in PRCM that define division and gate control for
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Power, Reset, and Clock Management
Introduction
421