Texas Instruments SimpleLink CC2620 Technical Reference Manual page 817

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10.1.6.2.3 Interrupts, Hardware, and Software Synchronization
This section describes the important relation of the RESULT_AVAIL interrupt activation and the data
writing completion of the DMAC inside the crypto core.
The RESULT_AVAIL interrupt is activated when the AHB master finishes the data write transfer from the
crypto core and the internal operation is completed. However, that does not ensure that data has been
written to the external memory, due to latency from the AHB master to the destination (typically a
memory). This latency might occur in the AHB bus subsystem outside of the crypto core, as this system
possibly contains bridges.
NOTE: If this latency can occur, the host must ensure (using a time-out or other synchronization
mechanisms) that external memory reads are only performed after all memory write
operations are finished.
10.1.6.3 Encryption and Decryption
The crypto engine (AES) transfers data over the following interfaces:
• AES accepts input data from two sources: AHB slave interface and DMA. Within one operation, it is
possible to combine data from these two sources: write data from the slave interface, and write data
from the DMA to complete the operation.
• Input IV and length must be supplied using the AHB slave interface. The output IV can be read using
the slave interface only.
• Result data must be read using the same interface as the input data: either using the slave interface or
DMA.
• The result tag for operations with authentication can be read using the slave interface or DMA.
SWCU117C – February 2015 – Revised September 2015
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AES Cryptoprocessor Overview
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