Fcfg1 Registers - Texas Instruments SimpleLink CC2620 Technical Reference Manual

Factory Configuration (FCFG)

9.2.1 FCFG1 Registers

Table 9-24 lists the memory-mapped registers for the FCFG1. All register offset addresses not listed in
Table 9-24 must be considered as reserved locations and the register contents must not be modified.
Offset Acronym
A0h MISC_CONF_1
C4h CONFIG_RF_FRONTEND_DIV5
C8h CONFIG_RF_FRONTEND_DIV6
CCh CONFIG_RF_FRONTEND_DIV10
D0h CONFIG_RF_FRONTEND_DIV12
D4h CONFIG_RF_FRONTEND_DIV15
D8h CONFIG_RF_FRONTEND_DIV30
DCh CONFIG_SYNTH_DIV5
E0h CONFIG_SYNTH_DIV6
E4h CONFIG_SYNTH_DIV10
E8h CONFIG_SYNTH_DIV12
ECh CONFIG_SYNTH_DIV15
F0h CONFIG_SYNTH_DIV30
F4h CONFIG_MISC_ADC_DIV5
F8h CONFIG_MISC_ADC_DIV6
FCh CONFIG_MISC_ADC_DIV10
100h CONFIG_MISC_ADC_DIV12
104h CONFIG_MISC_ADC_DIV15
108h CONFIG_MISC_ADC_DIV30
118h SHDW_DIE_ID_0
11Ch SHDW_DIE_ID_1
120h SHDW_DIE_ID_2
124h SHDW_DIE_ID_3
138h SHDW_OSC_BIAS_LDO_TRIM
13Ch SHDW_ANA_TRIM
164h FLASH_NUMBER
16Ch FLASH_COORDINATE
170h FLASH_E_P
174h FLASH_C_E_P_R
178h FLASH_P_R_PV
17Ch FLASH_EH_SEQ
180h FLASH_VHV_E
184h FLASH_PP
188h FLASH_PROG_EP
18Ch FLASH_ERA_PW
190h FLASH_VHV
194h FLASH_VHV_PV
198h FLASH_V
294h USER_ID
2B0h FLASH_OTP_DATA3
2B4h ANA2_TRIM
2B8h LDO_TRIM
2E8h MAC_BLE_0
718
Device Configuration
Table 9-24. FCFG1 Registers
Register Name
Misc configurations
Configuration of RF Frontend in Divide-by-5 Mode
Configuration of RF Frontend in Divide-by-6 Mode
Configuration of RF Frontend in Divide-by-10 Mode
Configuration of RF Frontend in Divide-by-12 Mode
Configuration of RF Frontend in Divide-by-15 Mode
Configuration of RF Frontend in Divide-by-30 Mode
Configuration of Synthesizer in Divide-by-5 Mode
Configuration of Synthesizer in Divide-by-6 Mode
Configuration of Synthesizer in Divide-by-10 Mode
Configuration of Synthesizer in Divide-by-12 Mode
Configuration of Synthesizer in Divide-by-15 Mode
Configuration of Synthesizer in Divide-by-30 Mode
Configuration of IFADC in Divide-by-5 Mode
Configuration of IFADC in Divide-by-6 Mode
Configuration of IFADC in Divide-by-10 Mode
Configuration of IFADC in Divide-by-12 Mode
Configuration of IFADC in Divide-by-15 Mode
Configuration of IFADC in Divide-by-30 Mode
Shadow of [JTAG_TAP::EFUSE:DIE_ID_0.*]
Shadow of [JTAG_TAP::EFUSE:DIE_ID_1.*]
Shadow of [JTAG_TAP::EFUSE:DIE_ID_2.*]
Shadow of [JTAG_TAP::EFUSE:DIE_ID_3.*]
Shadow of
[JTAG_TAP::EFUSE:OSC_BIAS_LDO_TRIM.*]
Shadow of [JTAG_TAP::EFUSE:ANA_TRIM.*]
Flash Erase and Program Setup Time
Flash Compaction, Execute, Program and Read
Flash Program, Read, and Program Verify
Flash Erase Hold and Sequence
Flash VHV Erase
Flash Program Pulse
Flash Program and Erase Pulse
Flash Erase Pulse Width
Flash VHV
Flash VHV Program Verify
Flash Voltages
User Identification.
Flash OTP Data 3
Misc Analog Trim
LDO Trim
MAC BLE Address 0
Copyright © 2015, Texas Instruments Incorporated
SWCU117C – February 2015 – Revised September 2015
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Section
Section 9.2.1.1
Section 9.2.1.2
Section 9.2.1.3
Section 9.2.1.4
Section 9.2.1.5
Section 9.2.1.6
Section 9.2.1.7
Section 9.2.1.8
Section 9.2.1.9
Section 9.2.1.10
Section 9.2.1.11
Section 9.2.1.12
Section 9.2.1.13
Section 9.2.1.14
Section 9.2.1.15
Section 9.2.1.16
Section 9.2.1.17
Section 9.2.1.18
Section 9.2.1.19
Section 9.2.1.20
Section 9.2.1.21
Section 9.2.1.22
Section 9.2.1.23
Section 9.2.1.24
Section 9.2.1.25
Section 9.2.1.26
Section 9.2.1.27
Section 9.2.1.28
Section 9.2.1.29
Section 9.2.1.30
Section 9.2.1.31
Section 9.2.1.32
Section 9.2.1.33
Section 9.2.1.34
Section 9.2.1.35
Section 9.2.1.36
Section 9.2.1.37
Section 9.2.1.38
Section 9.2.1.39
Section 9.2.1.40
Section 9.2.1.41
Section 9.2.1.42
Section 9.2.1.43