Texas Instruments SimpleLink CC2620 Technical Reference Manual page 166

Cortex-M3 Processor Registers
2.7.4.27 ICSR Register (Offset = D04h) [reset = X]
ICSR is shown in Figure 2-97
Interrupt Control State
This register is used to set a pending Non-Maskable Interrupt (NMI), set or clear a pending SVC, set or
clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority
pended exception, and check the vector number of the active exception.
31 30
NMIPENDSET RESERVED
R/W-0h
23 22
ISRPREEMPT ISRPENDING
R-0h R-0h
15 14
VECTPENDING
7 6
Bit Field
31 NMIPENDSET
30-29 RESERVED
28 PENDSVSET
27 PENDSVCLR
26 PENDSTSET
25 PENDSTCLR
24 RESERVED
23 ISRPREEMPT
22 ISRPENDING
21-18 RESERVED
17-12 VECTPENDING
166
and described in
Figure 2-97. ICSR Register
29 28
PENDSVSET
R/W-0h R/W-0h
21 20
13 12
R-0h
5 4
Table 2-123. ICSR Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 0h
W X
R/W 0h
W X
R 0h
R 0h
R 0h
R 0h
R 0h
Copyright © 2015, Texas Instruments Incorporated
Table 2-123.
27
PENDSVCLR PENDSTSET
W-X R/W-0h
19
RESERVED
R-0h
11
RETTOBASE
R-0h
3
VECTACTIVE
R-0h
Description
Set pending NMI bit. Setting this bit pends and activates an NMI.
Because NMI is the highest-priority interrupt, it takes effect as soon
as it registers.
0: No action
1: Set pending NMI
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Set pending pendSV bit.
0: No action
1: Set pending PendSV
Clear pending pendSV bit
0: No action
1: Clear pending pendSV
Set a pending SysTick bit.
0: No action
1: Set pending SysTick
Clear pending SysTick bit
0: No action
1: Clear pending SysTick
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
This field can only be used at debug time. It indicates that a pending
interrupt is to be taken in the next running cycle. If
DHCSR.C_MASKINTS= 0, the interrupt is serviced.
0: A pending exception is not serviced.
1: A pending exception is serviced on exit from the debug halt state
Interrupt pending flag. Excludes NMI and faults.
0x0: Interrupt not pending
0x1: Interrupt pending
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Pending ISR number field. This field contains the interrupt number of
the highest priority pending ISR.
SWCU117C – February 2015 – Revised September 2015
26 25
PENDSTCLR RESERVED
W-X
18 17
VECTPENDING
R-0h
10 9
RESERVED VECTACTIVE
R-0h
2 1
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24
R-0h
16
8
R-0h
0