Texas Instruments SimpleLink CC2620 Technical Reference Manual page 150

Cortex-M3 Processor Registers
Table 2-109. NVIC_ICPR0 Register Field Descriptions (continued)
Bit Field
2 CLRPEND2
1 CLRPEND1
0 CLRPEND0
150
Type Reset Description
R/W 0h
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV
for details). Reading the bit returns its current state.
R/W 0h
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV
for details). Reading the bit returns its current state.
R/W 0h
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV
for details). Reading the bit returns its current state.
Copyright © 2015, Texas Instruments Incorporated
SWCU117C – February 2015 – Revised September 2015
Submit Documentation Feedback
www.ti.com