Vims Flash Line Buffering - Texas Instruments SimpleLink CC2620 Technical Reference Manual

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7.1.1.4 Split Mode
In split mode, the RAM block functions as two 4K 4-way random replacement caches for Flash block. One
cache for the CPU accesses the Flash SYSCODE address space, and another cache for the CPU
accesses the Flash USERCODE address space. The GPRAM space is not available in split mode. Also,
all system bus accesses to the Flash block are routed directly to the Flash block.
icode/dcode
sysbus

7.1.2 VIMS Flash Line Buffering

The VIMS module contains two flash line buffers because the flash word size is 64 bits.
• A line buffer is placed in the flash CPU bus path that is controlled by the VIMS:CTL.IDCODE_LB_DIS
register.
• A line buffer is placed in the flash system bus path that is controlled by the
VIMS:CTL.SYSBUS_LB_DIS register.
The objectives of the buffers are to prevent refetching the 32-bit part of the data that has already been
fetched (but not used) in a previous cycle. The status of the line buffers can be found in the
VIMS:STATUS.IDCODE_LB_DIS register and the VIMS:STATUS.SYSBUS_LB_DIS register.
7.1.3 VIMS Arbitration
The VIMS provides arbitration between the CPU bus and the system bus. The arbitration is configurable
between round-robin and static, through the VIMS:CTL.ARB_CFG register. The static arbitration is
enabled by default and gives the CPU priority over system bus accesses.
The system arbiter allows accesses to occur simultaneously, provided that the CPU bus and the system
bus have different target memories. If, for example, a CPU access causes a cache hit, a system bus
access can access the flash simultaneously.
7.1.4 VIMS Cache TAG Prefetch
The cache contains a TAG prefetch system that automatically prefetches the TAG data for the next 64-bit
address. This feature is controlled through the VIMS:CTL.PREF_EN register, and is only enabled if the
VIMS mode is set to cache mode. Any access using a prefetched TAG saves one CLK cycle in the access
because tag lookup can be skipped. A prefetch hit is defined as an access using prefetched TAG data and
data that is available in the cache.
TAG prefetch is mainly intended for performance optimization when the CPU is running at full speed. If the
CPU is not running at full speed, there is no performance optimization; therefore the TAG prefetch system
must be disabled.
SWCU117C – February 2015 – Revised September 2015
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Figure 7-6. VIMS Module in Split Mode
USERCODE and
SYSCODE
address space
CACHE
FLASH
USERCODE and
SYSCODE
address space
ROM
BROM
address space
Copyright © 2015, Texas Instruments Incorporated
VIMS Configurations
icode/dcode
sysbus
Versatile Instruction Memory System (VIMS)
537