Texas Instruments SimpleLink CC2620 Technical Reference Manual page 512

PRCM Registers
6.2.4.37 WARMRESET Register (Offset = 110h) [reset = 0h]
WARMRESET is shown in
WARM Reset Control And Status
31 30
23 22
15 14
7 6
Bit Field
31-3 RESERVED
2 WR_TO_PINRESET
1 LOCKUP_STAT
0 WDT_STAT
512
Power, Reset, and Clock Management
Figure 6-76 and described in
Figure 6-76. WARMRESET Register
29 28
RESERVED
R-0h
21 20
RESERVED
R-0h
13 12
RESERVED
R-0h
5 4
RESERVED
R-0h
Table 6-81. WARMRESET Register Field Descriptions
Type Reset
R 0h
R/W 0h
R 0h
R 0h
Copyright © 2015, Texas Instruments Incorporated
Table 6-81.
27 26
19 18
11 10
3 2
WR_TO_PINR
ESET
R/W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
0: No action
1: A warm system reset event triggered by the below listed sources
will result in an emulated pin reset.
Warm reset sources included:
ICEPick sysreset
System CPU reset request, CPU_SCS:AIRCR.SYSRESETREQ
System CPU Lockup
WDT timeout
An active ICEPick block system reset will gate all sources except
ICEPick sysreset
SW can read AON_SYSCTL:RESETCTL.RESET_SRC to find the
source of the last reset resulting in a full power up sequence.
WARMRESET in this register is set in the scenario that
WR_TO_PINRESET=1 and one of the above listed sources is
triggered.
0: No registred event
1: A system CPU LOCKUP event has occured since last SW clear of
the register.
A read of this register clears both WDT_STAT and LOCKUP_STAT.
0: No registered event
1: A WDT event has occured since last SW clear of the register.
A read of this register clears both WDT_STAT and LOCKUP_STAT.
SWCU117C – February 2015 – Revised September 2015
www.ti.com
25 24
17 16
9 8
1 0
LOCKUP_STA WDT_STAT
T
R-0h R-0h
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