Texas Instruments SimpleLink CC2620 Technical Reference Manual page 478

PRCM Registers
6.2.4.4 VDCTL Register (Offset = Ch) [reset = 0h]
VDCTL is shown in
MCU Voltage Domain Control
31 30
23 22
15 14
7 6
Bit Field
31-3 RESERVED
2 MCU_VD
1 RESERVED
0 ULDO
478
Power, Reset, and Clock Management
Figure 6-43 and described in
Figure 6-43. VDCTL Register
29 28
21 20
13 12
5 4
RESERVED
R/W-0h
Table 6-48. VDCTL Register Field Descriptions
Type Reset
R/W 0h
R/W 0h
R/W 0h
R/W 0h
Copyright © 2015, Texas Instruments Incorporated
Table 6-48.
27
RESERVED
R/W-0h
19
RESERVED
R/W-0h
11
RESERVED
R/W-0h
3
MCU_VD
R/W-0h
Description
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Request WUC to power down the MCU voltage domain
0: No request
1: Assert request when possible. An asserted power down request
will result in a boot of the MCU system when powered up again.
The bit will have no effect before the following requirements are met:
1. PDCTL1.CPU_ON = 0
2. PDCTL1.VIMS_MODE = 0
3. SECDMACLKGDS.DMA_CLK_EN = 0 (Note: Setting must be
loaded with CLKLOADCTL.LOAD)
4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 (Note: Setting must be
loaded with CLKLOADCTL.LOAD)
5. RFC do no request access to BUS
6. System CPU in deepsleep
Software must not rely on the value of a reserved. Writing any other
value than the reset value may result in undefined behavior.
Request WUC to switch to uLDO.
0: No request
1: Assert request when possible
The bit will have no effect before the following requirements are met:
1. PDCTL1.CPU_ON = 0
2. PDCTL1.VIMS_MODE = 0
3. SECDMACLKGDS.DMA_CLK_EN = 0 (Note: Setting must be
loaded with CLKLOADCTL.LOAD)
4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 (Note: Setting must be
loaded with CLKLOADCTL.LOAD)
5. RFC do no request access to BUS
6. System CPU in deepsleep
SWCU117C – February 2015 – Revised September 2015
26 25
18 17
10 9
2 1
RESERVED
R/W-0h
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24
16
8
0
ULDO
R/W-0h